3 * Functions for omap5 based boards.
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 * Sricharan <r.sricharan@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/armv7.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/sizes.h>
36 #include <asm/utils.h>
37 #include <asm/arch/gpio.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
43 static struct gpio_bank gpio_bank_54xx[6] = {
44 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
45 { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
46 { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
49 { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
52 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
54 #ifdef CONFIG_SPL_BUILD
56 * Some tuning of IOs for optimal power and performance
58 void do_io_settings(void)
60 u32 io_settings = 0, mask = 0;
61 struct omap_sys_ctrl_regs *ioregs_base =
62 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
64 /* Impedance settings EMMC, C2C 1,2, hsi2 */
65 mask = (ds_mask << 2) | (ds_mask << 8) |
66 (ds_mask << 16) | (ds_mask << 18);
67 io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
69 io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
70 (ds_45_ohm << 18) | (ds_60_ohm << 2);
71 writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
73 /* Impedance settings Mcspi2 */
74 mask = (ds_mask << 30);
75 io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
77 io_settings |= (ds_60_ohm << 30);
78 writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
80 /* Impedance settings C2C 3,4 */
81 mask = (ds_mask << 14) | (ds_mask << 16);
82 io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
84 io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
85 writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
87 /* Slew rate settings EMMC, C2C 1,2 */
88 mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
89 io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
91 io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
92 writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
94 /* Slew rate settings hsi2, Mcspi2 */
95 mask = (sc_mask << 24) | (sc_mask << 28);
96 io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
98 io_settings |= (sc_fast << 28) | (sc_fast << 24);
99 writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
101 /* Slew rate settings C2C 3,4 */
102 mask = (sc_mask << 16) | (sc_mask << 18);
103 io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
105 io_settings |= (sc_na << 16) | (sc_na << 18);
106 writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
108 /* impedance and slew rate settings for usb */
109 mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
110 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
111 io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
113 io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
114 (ds_60_ohm << 23) | (sc_fast << 20) |
115 (sc_fast << 17) | (sc_fast << 14);
116 writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
118 /* LPDDR2 io settings */
119 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
120 &(ioregs_base->control_ddrch1_0));
121 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
122 &(ioregs_base->control_ddrch1_1));
123 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
124 &(ioregs_base->control_ddrch2_0));
125 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
126 &(ioregs_base->control_ddrch2_1));
127 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
128 &(ioregs_base->control_lpddr2ch1_0));
129 writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
130 &(ioregs_base->control_lpddr2ch1_1));
131 writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
132 &(ioregs_base->control_ddrio_0));
133 writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
134 &(ioregs_base->control_ddrio_1));
135 writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
136 &(ioregs_base->control_ddrio_2));
139 writel(EFUSE_1, &(ioregs_base->control_efuse_1));
140 writel(EFUSE_2, &(ioregs_base->control_efuse_2));
141 writel(EFUSE_3, &(ioregs_base->control_efuse_3));
142 writel(EFUSE_4, &(ioregs_base->control_efuse_4));
146 void init_omap_revision(void)
149 * For some of the ES2/ES1 boards ID_CODE is not reliable:
150 * Also, ES1 and ES2 have different ARM revisions
151 * So use ARM revision for identification
153 unsigned int rev = cortex_rev();
156 case MIDR_CORTEX_A15_R0P0:
157 *omap_si_rev = OMAP5430_ES1_0;
160 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
164 void reset_cpu(ulong ignored)
166 u32 omap_rev = omap_revision();
169 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
170 * So use cold reset in case instead.
172 if (omap_rev == OMAP5430_ES1_0)
173 writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
175 writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);