3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/omap.h>
30 #include <asm/arch/sys_proto.h>
31 #include <asm/omap_common.h>
32 #include <asm/arch/clocks.h>
33 #include <asm/omap_gpio.h>
36 struct prcm_regs const **prcm =
37 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
38 struct dplls const **dplls_data =
39 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
40 struct vcores_data const **omap_vcores =
41 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
42 struct omap_sys_ctrl_regs const **ctrl =
43 (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
45 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
46 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
47 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
48 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
49 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
50 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
51 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
52 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
55 static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
56 {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
57 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
58 {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
59 {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
60 {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
61 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
62 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
65 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
66 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
75 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
76 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
77 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
78 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
79 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
80 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
81 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
82 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
85 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
86 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
87 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
88 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
89 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
90 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
91 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
92 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
95 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
96 {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
97 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
98 {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
99 {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
100 {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
101 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
102 {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
105 static const struct dpll_params
106 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
107 {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
109 {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
110 {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
111 {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
112 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
113 {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
116 static const struct dpll_params
117 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
118 {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
119 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
120 {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
121 {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
122 {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
123 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
124 {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
127 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
128 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
129 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
130 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
131 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
132 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
134 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
137 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
138 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
139 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
140 {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
141 {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
142 {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
144 {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
147 /* ABE M & N values with sys_clk as source */
148 static const struct dpll_params
149 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
150 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
151 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
152 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
153 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
154 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
155 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
156 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
159 /* ABE M & N values with 32K clock as source */
160 static const struct dpll_params abe_dpll_params_32k_196608khz = {
161 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
164 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
165 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
166 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
167 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
168 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
169 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
170 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
171 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
174 struct dplls omap5_dplls_es1 = {
175 .mpu = mpu_dpll_params_800mhz,
176 .core = core_dpll_params_2128mhz_ddr532,
177 .per = per_dpll_params_768mhz,
178 .iva = iva_dpll_params_2330mhz,
179 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
180 .abe = abe_dpll_params_sysclk_196608khz,
182 .abe = &abe_dpll_params_32k_196608khz,
184 .usb = usb_dpll_params_1920mhz
187 struct pmic_data palmas = {
188 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
189 .step = 10000, /* 10 mV represented in uV */
191 * Offset codes 1-6 all give the base voltage in Palmas
192 * Offset code 0 switches OFF the SMPS
197 struct vcores_data omap5430_volts = {
198 .mpu.value = VDD_MPU,
199 .mpu.addr = SMPS_REG_ADDR_12_MPU,
202 .core.value = VDD_CORE,
203 .core.addr = SMPS_REG_ADDR_8_CORE,
204 .core.pmic = &palmas,
207 .mm.addr = SMPS_REG_ADDR_45_IVA,
211 struct vcores_data omap5432_volts = {
212 .mpu.value = VDD_MPU_5432,
213 .mpu.addr = SMPS_REG_ADDR_12_MPU,
216 .core.value = VDD_CORE_5432,
217 .core.addr = SMPS_REG_ADDR_8_CORE,
218 .core.pmic = &palmas,
220 .mm.value = VDD_MM_5432,
221 .mm.addr = SMPS_REG_ADDR_45_IVA,
226 * Enable essential clock domains, modules and
227 * do some additional special settings needed
229 void enable_basic_clocks(void)
231 u32 const clk_domains_essential[] = {
232 (*prcm)->cm_l4per_clkstctrl,
233 (*prcm)->cm_l3init_clkstctrl,
234 (*prcm)->cm_memif_clkstctrl,
235 (*prcm)->cm_l4cfg_clkstctrl,
239 u32 const clk_modules_hw_auto_essential[] = {
240 (*prcm)->cm_l3_2_gpmc_clkctrl,
241 (*prcm)->cm_memif_emif_1_clkctrl,
242 (*prcm)->cm_memif_emif_2_clkctrl,
243 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
244 (*prcm)->cm_wkup_gpio1_clkctrl,
245 (*prcm)->cm_l4per_gpio2_clkctrl,
246 (*prcm)->cm_l4per_gpio3_clkctrl,
247 (*prcm)->cm_l4per_gpio4_clkctrl,
248 (*prcm)->cm_l4per_gpio5_clkctrl,
249 (*prcm)->cm_l4per_gpio6_clkctrl,
253 u32 const clk_modules_explicit_en_essential[] = {
254 (*prcm)->cm_wkup_gptimer1_clkctrl,
255 (*prcm)->cm_l3init_hsmmc1_clkctrl,
256 (*prcm)->cm_l3init_hsmmc2_clkctrl,
257 (*prcm)->cm_l4per_gptimer2_clkctrl,
258 (*prcm)->cm_wkup_wdtimer2_clkctrl,
259 (*prcm)->cm_l4per_uart3_clkctrl,
260 (*prcm)->cm_l4per_i2c1_clkctrl,
264 /* Enable optional additional functional clock for GPIO4 */
265 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
266 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
268 /* Enable 96 MHz clock for MMC1 & MMC2 */
269 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
270 HSMMC_CLKCTRL_CLKSEL_MASK);
271 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
272 HSMMC_CLKCTRL_CLKSEL_MASK);
274 /* Set the correct clock dividers for mmc */
275 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
276 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
277 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
278 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
280 /* Select 32KHz clock as the source of GPTIMER1 */
281 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
282 GPTIMER1_CLKCTRL_CLKSEL_MASK);
284 do_enable_clocks(clk_domains_essential,
285 clk_modules_hw_auto_essential,
286 clk_modules_explicit_en_essential,
289 /* Select 384Mhz for GPU as its the POR for ES1.0 */
290 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
291 CLKSEL_GPU_HYD_GCLK_MASK);
292 setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
293 CLKSEL_GPU_CORE_GCLK_MASK);
295 /* Enable SCRM OPT clocks for PER and CORE dpll */
296 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
297 OPTFCLKEN_SCRM_PER_MASK);
298 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
299 OPTFCLKEN_SCRM_CORE_MASK);
302 void enable_basic_uboot_clocks(void)
304 u32 const clk_domains_essential[] = {
308 u32 const clk_modules_hw_auto_essential[] = {
312 u32 const clk_modules_explicit_en_essential[] = {
313 (*prcm)->cm_l4per_mcspi1_clkctrl,
314 (*prcm)->cm_l4per_i2c2_clkctrl,
315 (*prcm)->cm_l4per_i2c3_clkctrl,
316 (*prcm)->cm_l4per_i2c4_clkctrl,
317 (*prcm)->cm_l3init_hsusbtll_clkctrl,
318 (*prcm)->cm_l3init_hsusbhost_clkctrl,
319 (*prcm)->cm_l3init_fsusb_clkctrl,
323 do_enable_clocks(clk_domains_essential,
324 clk_modules_hw_auto_essential,
325 clk_modules_explicit_en_essential,
330 * Enable non-essential clock domains, modules and
331 * do some additional special settings needed
333 void enable_non_essential_clocks(void)
335 u32 const clk_domains_non_essential[] = {
336 (*prcm)->cm_mpu_m3_clkstctrl,
337 (*prcm)->cm_ivahd_clkstctrl,
338 (*prcm)->cm_dsp_clkstctrl,
339 (*prcm)->cm_dss_clkstctrl,
340 (*prcm)->cm_sgx_clkstctrl,
341 (*prcm)->cm1_abe_clkstctrl,
342 (*prcm)->cm_c2c_clkstctrl,
343 (*prcm)->cm_cam_clkstctrl,
344 (*prcm)->cm_dss_clkstctrl,
345 (*prcm)->cm_sdma_clkstctrl,
349 u32 const clk_modules_hw_auto_non_essential[] = {
350 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
351 (*prcm)->cm_ivahd_ivahd_clkctrl,
352 (*prcm)->cm_ivahd_sl2_clkctrl,
353 (*prcm)->cm_dsp_dsp_clkctrl,
354 (*prcm)->cm_l3instr_l3_3_clkctrl,
355 (*prcm)->cm_l3instr_l3_instr_clkctrl,
356 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
357 (*prcm)->cm_l3init_hsi_clkctrl,
358 (*prcm)->cm_l4per_hdq1w_clkctrl,
362 u32 const clk_modules_explicit_en_non_essential[] = {
363 (*prcm)->cm1_abe_aess_clkctrl,
364 (*prcm)->cm1_abe_pdm_clkctrl,
365 (*prcm)->cm1_abe_dmic_clkctrl,
366 (*prcm)->cm1_abe_mcasp_clkctrl,
367 (*prcm)->cm1_abe_mcbsp1_clkctrl,
368 (*prcm)->cm1_abe_mcbsp2_clkctrl,
369 (*prcm)->cm1_abe_mcbsp3_clkctrl,
370 (*prcm)->cm1_abe_slimbus_clkctrl,
371 (*prcm)->cm1_abe_timer5_clkctrl,
372 (*prcm)->cm1_abe_timer6_clkctrl,
373 (*prcm)->cm1_abe_timer7_clkctrl,
374 (*prcm)->cm1_abe_timer8_clkctrl,
375 (*prcm)->cm1_abe_wdt3_clkctrl,
376 (*prcm)->cm_l4per_gptimer9_clkctrl,
377 (*prcm)->cm_l4per_gptimer10_clkctrl,
378 (*prcm)->cm_l4per_gptimer11_clkctrl,
379 (*prcm)->cm_l4per_gptimer3_clkctrl,
380 (*prcm)->cm_l4per_gptimer4_clkctrl,
381 (*prcm)->cm_l4per_mcspi2_clkctrl,
382 (*prcm)->cm_l4per_mcspi3_clkctrl,
383 (*prcm)->cm_l4per_mcspi4_clkctrl,
384 (*prcm)->cm_l4per_mmcsd3_clkctrl,
385 (*prcm)->cm_l4per_mmcsd4_clkctrl,
386 (*prcm)->cm_l4per_mmcsd5_clkctrl,
387 (*prcm)->cm_l4per_uart1_clkctrl,
388 (*prcm)->cm_l4per_uart2_clkctrl,
389 (*prcm)->cm_l4per_uart4_clkctrl,
390 (*prcm)->cm_wkup_keyboard_clkctrl,
391 (*prcm)->cm_wkup_wdtimer2_clkctrl,
392 (*prcm)->cm_cam_iss_clkctrl,
393 (*prcm)->cm_cam_fdif_clkctrl,
394 (*prcm)->cm_dss_dss_clkctrl,
395 (*prcm)->cm_sgx_sgx_clkctrl,
399 /* Enable optional functional clock for ISS */
400 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
402 /* Enable all optional functional clocks of DSS */
403 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
405 do_enable_clocks(clk_domains_non_essential,
406 clk_modules_hw_auto_non_essential,
407 clk_modules_explicit_en_non_essential,
410 /* Put camera module in no sleep mode */
411 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
412 MODULE_CLKCTRL_MODULEMODE_MASK,
413 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
414 MODULE_CLKCTRL_MODULEMODE_SHIFT);
417 void hw_data_init(void)
419 u32 omap_rev = omap_revision();
424 *prcm = &omap5_es1_prcm;
425 *dplls_data = &omap5_dplls_es1;
426 *omap_vcores = &omap5430_volts;
430 *prcm = &omap5_es1_prcm;
431 *dplls_data = &omap5_dplls_es1;
432 *omap_vcores = &omap5432_volts;
436 printf("\n INVALID OMAP REVISION ");