3 * HW data initialization for OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Sricharan R <r.sricharan@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/omap.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/arch/clock.h>
18 #include <asm/omap_gpio.h>
22 struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
24 struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
26 struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
28 struct omap_sys_ctrl_regs const **ctrl =
29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
31 /* OPP HIGH FREQUENCY for ES2.0 */
32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
42 /* OPP NOM FREQUENCY for ES1.0 */
43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
53 /* OPP LOW FREQUENCY for ES1.0 */
54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
64 /* OPP LOW FREQUENCY for ES2.0 */
65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
86 static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
97 static const struct dpll_params
98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
108 static const struct dpll_params
109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
119 static const struct dpll_params
120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
130 static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
163 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
191 /* ABE M & N values with sys_clk as source */
192 static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
203 /* ABE M & N values with 32K clock as source */
204 static const struct dpll_params abe_dpll_params_32k_196608khz = {
205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
209 static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
230 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
231 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
240 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
241 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
247 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
250 struct dplls omap5_dplls_es1 = {
251 .mpu = mpu_dpll_params_800mhz,
252 .core = core_dpll_params_2128mhz_ddr532,
253 .per = per_dpll_params_768mhz,
254 .iva = iva_dpll_params_2330mhz,
255 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
256 .abe = abe_dpll_params_sysclk_196608khz,
258 .abe = &abe_dpll_params_32k_196608khz,
260 .usb = usb_dpll_params_1920mhz,
264 struct dplls omap5_dplls_es2 = {
265 .mpu = mpu_dpll_params_1ghz,
266 .core = core_dpll_params_2128mhz_ddr532_es2,
267 .per = per_dpll_params_768mhz_es2,
268 .iva = iva_dpll_params_2330mhz,
269 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
270 .abe = abe_dpll_params_sysclk_196608khz,
272 .abe = &abe_dpll_params_32k_196608khz,
274 .usb = usb_dpll_params_1920mhz,
278 struct dplls dra7xx_dplls = {
279 .mpu = mpu_dpll_params_1ghz,
280 .core = core_dpll_params_2128mhz_dra7xx,
281 .per = per_dpll_params_768mhz_dra7xx,
282 .abe = abe_dpll_params_sysclk2_361267khz,
283 .iva = iva_dpll_params_2330mhz_dra7xx,
284 .usb = usb_dpll_params_1920mhz,
285 .ddr = ddr_dpll_params_2128mhz,
286 .gmac = gmac_dpll_params_2000mhz,
289 struct pmic_data palmas = {
290 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
291 .step = 10000, /* 10 mV represented in uV */
293 * Offset codes 1-6 all give the base voltage in Palmas
294 * Offset code 0 switches OFF the SMPS
297 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
298 .pmic_bus_init = sri2c_init,
299 .pmic_write = omap_vc_bypass_send_value,
302 struct pmic_data tps659038 = {
303 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
304 .step = 10000, /* 10 mV represented in uV */
306 * Offset codes 1-6 all give the base voltage in Palmas
307 * Offset code 0 switches OFF the SMPS
310 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
311 .pmic_bus_init = gpi2c_init,
312 .pmic_write = palmas_i2c_write_u8,
315 struct vcores_data omap5430_volts = {
316 .mpu.value = VDD_MPU,
317 .mpu.addr = SMPS_REG_ADDR_12_MPU,
320 .core.value = VDD_CORE,
321 .core.addr = SMPS_REG_ADDR_8_CORE,
322 .core.pmic = &palmas,
325 .mm.addr = SMPS_REG_ADDR_45_IVA,
329 struct vcores_data omap5430_volts_es2 = {
330 .mpu.value = VDD_MPU_ES2,
331 .mpu.addr = SMPS_REG_ADDR_12_MPU,
334 .core.value = VDD_CORE_ES2,
335 .core.addr = SMPS_REG_ADDR_8_CORE,
336 .core.pmic = &palmas,
338 .mm.value = VDD_MM_ES2,
339 .mm.addr = SMPS_REG_ADDR_45_IVA,
343 struct vcores_data dra752_volts = {
344 .mpu.value = VDD_MPU_DRA752,
345 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
346 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
347 .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
348 .mpu.pmic = &tps659038,
350 .eve.value = VDD_EVE_DRA752,
351 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
352 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
353 .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
354 .eve.pmic = &tps659038,
356 .gpu.value = VDD_GPU_DRA752,
357 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
358 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
359 .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
360 .gpu.pmic = &tps659038,
362 .core.value = VDD_CORE_DRA752,
363 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
364 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
365 .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
366 .core.pmic = &tps659038,
368 .iva.value = VDD_IVA_DRA752,
369 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
370 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
371 .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
372 .iva.pmic = &tps659038,
376 * Enable essential clock domains, modules and
377 * do some additional special settings needed
379 void enable_basic_clocks(void)
381 u32 const clk_domains_essential[] = {
382 (*prcm)->cm_l4per_clkstctrl,
383 (*prcm)->cm_l3init_clkstctrl,
384 (*prcm)->cm_memif_clkstctrl,
385 (*prcm)->cm_l4cfg_clkstctrl,
386 #ifdef CONFIG_DRIVER_TI_CPSW
387 (*prcm)->cm_gmac_clkstctrl,
392 u32 const clk_modules_hw_auto_essential[] = {
393 (*prcm)->cm_l3_gpmc_clkctrl,
394 (*prcm)->cm_memif_emif_1_clkctrl,
395 (*prcm)->cm_memif_emif_2_clkctrl,
396 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
397 (*prcm)->cm_wkup_gpio1_clkctrl,
398 (*prcm)->cm_l4per_gpio2_clkctrl,
399 (*prcm)->cm_l4per_gpio3_clkctrl,
400 (*prcm)->cm_l4per_gpio4_clkctrl,
401 (*prcm)->cm_l4per_gpio5_clkctrl,
402 (*prcm)->cm_l4per_gpio6_clkctrl,
403 (*prcm)->cm_l4per_gpio7_clkctrl,
404 (*prcm)->cm_l4per_gpio8_clkctrl,
408 u32 const clk_modules_explicit_en_essential[] = {
409 (*prcm)->cm_wkup_gptimer1_clkctrl,
410 (*prcm)->cm_l3init_hsmmc1_clkctrl,
411 (*prcm)->cm_l3init_hsmmc2_clkctrl,
412 (*prcm)->cm_l4per_gptimer2_clkctrl,
413 (*prcm)->cm_wkup_wdtimer2_clkctrl,
414 (*prcm)->cm_l4per_uart3_clkctrl,
415 (*prcm)->cm_l4per_i2c1_clkctrl,
416 #ifdef CONFIG_DRIVER_TI_CPSW
417 (*prcm)->cm_gmac_gmac_clkctrl,
420 #ifdef CONFIG_TI_QSPI
421 (*prcm)->cm_l4per_qspi_clkctrl,
426 /* Enable optional additional functional clock for GPIO4 */
427 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
428 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
430 /* Enable 96 MHz clock for MMC1 & MMC2 */
431 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
432 HSMMC_CLKCTRL_CLKSEL_MASK);
433 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
434 HSMMC_CLKCTRL_CLKSEL_MASK);
436 /* Set the correct clock dividers for mmc */
437 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
438 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
439 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
440 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
442 /* Select 32KHz clock as the source of GPTIMER1 */
443 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
444 GPTIMER1_CLKCTRL_CLKSEL_MASK);
446 do_enable_clocks(clk_domains_essential,
447 clk_modules_hw_auto_essential,
448 clk_modules_explicit_en_essential,
451 #ifdef CONFIG_TI_QSPI
452 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
455 /* Enable SCRM OPT clocks for PER and CORE dpll */
456 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
457 OPTFCLKEN_SCRM_PER_MASK);
458 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
459 OPTFCLKEN_SCRM_CORE_MASK);
462 void enable_basic_uboot_clocks(void)
464 u32 const clk_domains_essential[] = {
468 u32 const clk_modules_hw_auto_essential[] = {
469 (*prcm)->cm_l3init_hsusbtll_clkctrl,
473 u32 const clk_modules_explicit_en_essential[] = {
474 (*prcm)->cm_l4per_mcspi1_clkctrl,
475 (*prcm)->cm_l4per_i2c2_clkctrl,
476 (*prcm)->cm_l4per_i2c3_clkctrl,
477 (*prcm)->cm_l4per_i2c4_clkctrl,
478 (*prcm)->cm_l4per_i2c5_clkctrl,
479 (*prcm)->cm_l3init_hsusbhost_clkctrl,
480 (*prcm)->cm_l3init_fsusb_clkctrl,
483 do_enable_clocks(clk_domains_essential,
484 clk_modules_hw_auto_essential,
485 clk_modules_explicit_en_essential,
489 const struct ctrl_ioregs ioregs_omap5430 = {
490 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
491 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
492 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
493 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
494 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
497 const struct ctrl_ioregs ioregs_omap5432_es1 = {
498 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
499 .ctrl_lpddr2ch = 0x0,
500 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
501 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
502 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
503 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
504 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
505 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
508 const struct ctrl_ioregs ioregs_omap5432_es2 = {
509 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
510 .ctrl_lpddr2ch = 0x0,
511 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
512 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
513 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
514 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
515 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
516 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
519 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
520 .ctrl_ddrch = 0x40404040,
521 .ctrl_lpddr2ch = 0x40404040,
522 .ctrl_ddr3ch = 0x80808080,
523 .ctrl_ddrio_0 = 0xA2084210,
524 .ctrl_ddrio_1 = 0x84210840,
525 .ctrl_ddrio_2 = 0x84210000,
526 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
527 .ctrl_emif_sdram_config_ext_final = 0x000101A7,
528 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
531 void hw_data_init(void)
533 u32 omap_rev = omap_revision();
539 *prcm = &omap5_es1_prcm;
540 *dplls_data = &omap5_dplls_es1;
541 *omap_vcores = &omap5430_volts;
547 *prcm = &omap5_es2_prcm;
548 *dplls_data = &omap5_dplls_es2;
549 *omap_vcores = &omap5430_volts_es2;
555 *prcm = &dra7xx_prcm;
556 *dplls_data = &dra7xx_dplls;
557 *omap_vcores = &dra752_volts;
558 *ctrl = &dra7xx_ctrl;
562 printf("\n INVALID OMAP REVISION ");
566 void get_ioregs(const struct ctrl_ioregs **regs)
568 u32 omap_rev = omap_revision();
573 *regs = &ioregs_omap5430;
576 *regs = &ioregs_omap5432_es1;
579 *regs = &ioregs_omap5432_es2;
583 *regs = &ioregs_dra7xx_es1;
587 printf("\n INVALID OMAP REVISION ");