3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/mem.h>
31 #include <asm/arch/sys_proto.h>
34 struct gpmc *gpmc_cfg;
36 #if defined(CONFIG_CMD_NAND)
37 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
43 M_NAND_GPMC_CONFIG6, 0
46 #if defined(CONFIG_ENV_IS_IN_NAND)
54 #if defined(CONFIG_CMD_ONENAND)
55 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
61 ONENAND_GPMC_CONFIG6, 0
64 #if defined(CONFIG_ENV_IS_IN_ONENAND)
72 /********************************************************
73 * mem_ok() - test used to see if timings are correct
74 * for a part. Helps in guessing which part
75 * we are currently using.
76 *******************************************************/
80 u32 pattern = 0x12345678;
82 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
84 writel(0x0, addr + 0x400); /* clear pos A */
85 writel(pattern, addr); /* pattern to pos B */
86 writel(0x0, addr + 4); /* remove pattern off the bus */
87 val1 = readl(addr + 0x400); /* get pos A value */
88 val2 = readl(addr); /* get val2 */
89 writel(0x0, addr + 0x400); /* clear pos A */
91 if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
97 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
100 writel(0, &cs->config7);
102 /* Delay for settling */
103 writel(gpmc_config[0], &cs->config1);
104 writel(gpmc_config[1], &cs->config2);
105 writel(gpmc_config[2], &cs->config3);
106 writel(gpmc_config[3], &cs->config4);
107 writel(gpmc_config[4], &cs->config5);
108 writel(gpmc_config[5], &cs->config6);
111 * Enable the config. size is the CS size and goes in
112 * bits 11:8. We set bit 6 to enable this CS and the base
113 * address goes into bits 5:0.
115 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
116 ((base >> 24) & GPMC_BASEADDR_MASK),
121 /*****************************************************
122 * gpmc_init(): init gpmc bus
123 * Init GPMC for x16, MuxMode (SDRAM in x32).
124 * This code can only be executed from SRAM or SDRAM.
125 *****************************************************/
128 /* putting a blanket check on GPMC based on ZeBu for now */
129 gpmc_cfg = (struct gpmc *)GPMC_BASE;
130 #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
131 const u32 *gpmc_config = NULL;
137 /* global settings */
138 writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
139 writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
141 config = readl(&gpmc_cfg->config);
143 writel(config, &gpmc_cfg->config);
146 * Disable the GPMC0 config set by ROM code
147 * It conflicts with our MPDB (both at 0x08000000)
149 writel(0, &gpmc_cfg->cs[0].config7);
152 #if defined(CONFIG_CMD_NAND) /* CS 0 */
153 gpmc_config = gpmc_m_nand;
155 base = PISMO1_NAND_BASE;
156 size = PISMO1_NAND_SIZE;
157 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
160 #if defined(CONFIG_CMD_ONENAND)
161 gpmc_config = gpmc_onenand;
162 base = PISMO1_ONEN_BASE;
163 size = PISMO1_ONEN_SIZE;
164 enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);