2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/mem.h>
16 #include <asm/arch/clocks_omap3.h>
17 #include <linux/linkage.h>
19 #ifdef CONFIG_SPL_BUILD
20 ENTRY(save_boot_params)
21 ldr r4, =omap3_boot_device
25 b save_boot_params_ret
26 ENDPROC(save_boot_params)
30 * Funtion for making PPA HAL API calls in secure devices
35 ENTRY(do_omap3_emu_romcode_call)
36 PUSH {r4-r12, lr} @ Save all registers from ROM code!
37 MOV r12, r0 @ Copy the Secure Service ID in R12
38 MOV r3, r1 @ Copy the pointer to va_list in R3
39 MOV r1, #0 @ Process ID - 0
40 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
42 MOV r6, #0xFF @ Indicate new Task call
43 mcr p15, 0, r0, c7, c10, 4 @ DSB
44 mcr p15, 0, r0, c7, c10, 5 @ DMB
45 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
46 @ because we use -march=armv5
48 ENDPROC(do_omap3_emu_romcode_call)
50 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
51 /**************************************************************************
52 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
53 * R1 = SRAM destination address.
54 *************************************************************************/
56 /* Copy DPLL code into SRAM */
57 adr r0, go_to_speed /* copy from start of go_to_speed... */
58 adr r2, lowlevel_init /* ... up to start of low_level_init */
60 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
61 stmia r1!, {r3 - r10} /* copy to target address [r1] */
62 cmp r0, r2 /* until source end address [r2] */
64 mov pc, lr /* back to caller */
67 /* ***************************************************************************
68 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
69 * -executed from SRAM.
70 * R0 = CM_CLKEN_PLL-bypass value
71 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
72 * R2 = CM_CLKSEL_CORE-divider values
73 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
75 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
76 * confused. A reset of the controller gets it back. Taking away its
77 * L3 when its not in self refresh seems bad for it. Normally, this
78 * code runs from flash before SDR is init so that should be ok.
79 ****************************************************************************/
83 /* move into fast relock bypass */
87 ldr r5, [r3] /* get status */
88 and r5, r5, #0x1 /* isolate core status */
89 cmp r5, #0x1 /* still locked? */
90 beq wait1 /* if lock, loop */
92 /* set new dpll dividers _after_ in bypass */
94 str r1, [r5] /* set m, n, m2 */
96 str r2, [r5] /* set l3/l4/.. dividers*/
97 ldr r5, pll_div_add3 /* wkup */
98 ldr r2, pll_div_val3 /* rsm val */
100 ldr r5, pll_div_add4 /* gfx */
103 ldr r5, pll_div_add5 /* emu */
107 /* now prepare GPMC (flash) for new dpll speed */
108 /* flash needs to be stable when we jump back to it */
109 ldr r5, flash_cfg3_addr
110 ldr r2, flash_cfg3_val
112 ldr r5, flash_cfg4_addr
113 ldr r2, flash_cfg4_val
115 ldr r5, flash_cfg5_addr
116 ldr r2, flash_cfg5_val
118 ldr r5, flash_cfg1_addr
120 orr r2, r2, #0x3 /* up gpmc divider */
123 /* lock DPLL3 and wait a bit */
124 orr r0, r0, #0x7 /* set up for lock mode */
125 str r0, [r4] /* lock */
126 nop /* ARM slow at this point working at sys_clk */
131 ldr r5, [r3] /* get status */
132 and r5, r5, #0x1 /* isolate core status */
133 cmp r5, #0x1 /* still locked? */
134 bne wait2 /* if lock, loop */
140 mov pc, lr /* back to caller, locked */
143 _go_to_speed: .word go_to_speed
145 /* these constants need to be close for PIC code */
146 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
148 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
150 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
152 .word STNOR_GPMC_CONFIG3
154 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
156 .word STNOR_GPMC_CONFIG4
158 .word STNOR_GPMC_CONFIG5
160 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
170 .word (WKUP_RSM << 1)
184 str ip, [sp] /* stash ip register */
185 mov ip, lr /* save link reg across call */
186 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
188 * No need to copy/exec the clock code - DPLL adjust already done
189 * in NAND/oneNAND Boot.
191 ldr r1, =SRAM_CLK_CODE
193 #endif /* NAND Boot */
194 mov lr, ip /* restore link reg */
195 ldr ip, [sp] /* restore save ip */
196 /* tail-call s_init to setup pll, mux, memory */
199 ENDPROC(lowlevel_init)
201 /* the literal pools origin */
207 .word LOW_LEVEL_SRAM_STACK
209 /* DPLL(1-4) PARAM TABLES */
212 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
213 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
214 * The values are defined for all possible sysclk and for ES1 and ES2.
220 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
222 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
224 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
228 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
230 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
232 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
236 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
238 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
240 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
244 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
246 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
248 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
252 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
254 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
256 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
259 .globl get_mpu_dpll_param
261 adr r0, mpu_dpll_param
267 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
269 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
271 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
275 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
277 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
279 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
283 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
285 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
287 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
291 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
293 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
295 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
299 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
301 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
303 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
306 .globl get_iva_dpll_param
308 adr r0, iva_dpll_param
311 /* Core DPLL targets for L3 at 166 & L133 */
315 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
317 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
319 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
323 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
325 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
327 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
331 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
333 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
335 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
339 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
341 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
343 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
347 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
349 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
351 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
353 .globl get_core_dpll_param
355 adr r0, core_dpll_param
358 /* PER DPLL values are same for both ES1 and ES2 */
361 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
364 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
367 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
370 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
373 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
375 .globl get_per_dpll_param
377 adr r0, per_dpll_param
380 /* PER2 DPLL values */
383 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
386 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
389 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
392 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
395 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
397 .globl get_per2_dpll_param
399 adr r0, per2_dpll_param
403 * Tables for 36XX/37XX devices
443 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
444 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
445 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
446 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
447 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
448 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
452 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
454 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
456 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
458 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
460 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
463 ENTRY(get_36x_mpu_dpll_param)
464 adr r0, mpu_36x_dpll_param
466 ENDPROC(get_36x_mpu_dpll_param)
468 ENTRY(get_36x_iva_dpll_param)
469 adr r0, iva_36x_dpll_param
471 ENDPROC(get_36x_iva_dpll_param)
473 ENTRY(get_36x_core_dpll_param)
474 adr r0, core_36x_dpll_param
476 ENDPROC(get_36x_core_dpll_param)
478 ENTRY(get_36x_per_dpll_param)
479 adr r0, per_36x_dpll_param
481 ENDPROC(get_36x_per_dpll_param)
483 ENTRY(get_36x_per2_dpll_param)
484 adr r0, per2_36x_dpll_param
486 ENDPROC(get_36x_per2_dpll_param)