3 * Vaibhav Hiremath <hvaibhav@ti.com>
5 * Based on mem.c and sdrc.c
8 * Texas Instruments Incorporated - http://www.ti.com/
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/emif4.h>
32 extern omap3_sysinfo sysinfo;
34 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
38 * - Return 1 if mem type in use is SDR
47 * - Get size of chip select 0/1
49 u32 get_sdr_cs_size(u32 cs)
53 /* TODO: Calculate the size based on EMIF4 configuration */
54 size = CONFIG_SYS_CS0_SIZE;
61 * - Get offset of cs from cs0 start
63 u32 get_sdr_cs_offset(u32 cs)
72 * - Init the emif4 module for DDR access
73 * - Early init routines, called from flash or SRAM.
75 void do_emif4_init(void)
78 /* Set the DDR PHY parameters in PHY ctrl registers */
79 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
80 EMIF4_DDR1_EXT_STRB_DIS);
81 writel(regval, &emif4_base->ddr_phyctrl1);
82 writel(regval, &emif4_base->ddr_phyctrl1_shdw);
83 writel(0, &emif4_base->ddr_phyctrl2);
85 /* Reset the DDR PHY and wait till completed */
86 regval = readl(&emif4_base->sdram_iodft_tlgc);
88 writel(regval, &emif4_base->sdram_iodft_tlgc);
89 /*Wait till that bit clears*/
90 while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
91 /*Re-verify the DDR PHY status*/
92 while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
95 writel(regval, &emif4_base->sdram_iodft_tlgc);
96 /* Set SDR timing registers */
97 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
98 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
99 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
101 writel(regval, &emif4_base->sdram_time1);
102 writel(regval, &emif4_base->sdram_time1_shdw);
104 regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
105 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
106 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
107 writel(regval, &emif4_base->sdram_time2);
108 writel(regval, &emif4_base->sdram_time2_shdw);
110 regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
111 writel(regval, &emif4_base->sdram_time3);
112 writel(regval, &emif4_base->sdram_time3_shdw);
114 /* Set the PWR control register */
115 regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
116 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
117 writel(regval, &emif4_base->sdram_pwr_mgmt);
118 writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
120 /* Set the DDR refresh rate control register */
121 regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
122 writel(regval, &emif4_base->sdram_refresh_ctrl);
123 writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
125 /* set the SDRAM configuration register */
126 regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
127 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
128 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
129 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
130 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
131 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
132 writel(regval, &emif4_base->sdram_config);
137 * - Sets uboots idea of sdram size
141 DECLARE_GLOBAL_DATA_PTR;
142 unsigned int size0 = 0, size1 = 0;
144 size0 = get_sdr_cs_size(CS0);
146 * If a second bank of DDR is attached to CS1 this is
147 * where it can be started. Early init code will init
150 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
151 size1 = get_sdr_cs_size(CS1);
153 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
154 gd->bd->bi_dram[0].size = size0;
155 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
156 gd->bd->bi_dram[1].size = size1;
163 * - Initialize memory subsystem