3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clocks_omap3.h>
19 #include <asm/arch/mem.h>
20 #include <asm/arch/sys_proto.h>
21 #include <environment.h>
25 * sr32 - clear & set a value in a bit range for a 32 bit address
27 static inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
32 tmp = readl((u32)addr) & ~(msk << start_bit);
33 tmp |= value << start_bit;
34 writel(tmp, (u32)addr);
37 /******************************************************************************
38 * get_sys_clk_speed() - determine reference oscillator speed
39 * based on known 32kHz clock and gptimer.
40 *****************************************************************************/
41 u32 get_osc_clk_speed(void)
43 u32 start, cstart, cend, cdiff, cdiv, val;
44 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
45 struct prm *prm_base = (struct prm *)PRM_BASE;
46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
47 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
49 val = readl(&prm_base->clksrc_ctrl);
51 if (val & SYSCLKDIV_2)
57 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
59 /* select sys_clk for GPT1 */
60 writel(val, &prcm_base->clksel_wkup);
62 /* Enable I and F Clocks for GPT1 */
63 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
64 writel(val, &prcm_base->iclken_wkup);
66 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
67 writel(val, &prcm_base->fclken_wkup);
69 writel(0, &gpt1_base->tldr); /* start counting at 0 */
70 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
72 /* enable 32kHz source, determine sys_clk via gauging */
74 /* start time in 20 cycles */
75 start = 20 + readl(&s32k_base->s32k_cr);
77 /* dead loop till start time */
78 while (readl(&s32k_base->s32k_cr) < start);
80 /* get start sys_clk count */
81 cstart = readl(&gpt1_base->tcrr);
83 /* wait for 40 cycles */
84 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
85 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
86 cdiff = cend - cstart; /* get elapsed ticks */
89 /* based on number of ticks assign speed */
92 else if (cdiff > 15200)
94 else if (cdiff > 13000)
96 else if (cdiff > 9000)
98 else if (cdiff > 7600)
104 /******************************************************************************
105 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
106 * input oscillator clock frequency.
107 *****************************************************************************/
108 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
130 * OMAP34XX/35XX specific functions
133 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
135 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
136 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
137 void (*f_lock_pll) (u32, u32, u32, u32);
138 int xip_safe, p0, p1, p2, p3;
140 xip_safe = is_running_in_sram();
142 /* Moving to the right sysclk and ES rev base */
143 ptr = ptr + (3 * clk_index) + sil_index;
148 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
150 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
151 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
155 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
156 * work. write another value and then default value.
159 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
160 sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
161 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
163 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
164 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
166 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
167 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
169 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
170 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
172 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
173 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
176 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
178 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
180 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
182 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
184 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
186 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
187 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
188 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
190 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
194 } else if (is_running_in_flash()) {
196 * if running from flash, jump to small relocated code
199 f_lock_pll = (void *) (SRAM_CLK_CODE);
201 p0 = readl(&prcm_base->clken_pll);
202 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
203 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
204 sr32(&p0, 4, 4, ptr->fsel);
206 p1 = readl(&prcm_base->clksel1_pll);
207 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
208 sr32(&p1, 27, 5, ptr->m2);
209 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
210 sr32(&p1, 16, 11, ptr->m);
211 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
212 sr32(&p1, 8, 7, ptr->n);
213 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
216 p2 = readl(&prcm_base->clksel_core);
218 sr32(&p2, 8, 4, CORE_SSI_DIV);
220 sr32(&p2, 4, 2, CORE_FUSB_DIV);
222 sr32(&p2, 2, 2, CORE_L4_DIV);
224 sr32(&p2, 0, 2, CORE_L3_DIV);
226 p3 = (u32)&prcm_base->idlest_ckgen;
228 (*f_lock_pll) (p0, p1, p2, p3);
232 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
234 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
235 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
237 /* Moving it to the right sysclk base */
238 ptr = ptr + clk_index;
240 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
241 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
242 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
245 * Errata 1.50 Workaround for OMAP3 ES1.0 only
246 * If using default divisors, write default divisor + 1
247 * and then the actual divisor value
250 sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
251 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
253 sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
254 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
256 sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
257 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
259 sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
260 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
261 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
262 sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
263 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
266 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
267 sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
269 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
270 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
272 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
273 sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
275 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
276 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
277 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
280 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
282 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
283 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
285 /* Moving it to the right sysclk base */
286 ptr = ptr + clk_index;
288 /* PER2 DPLL (DPLL5) */
289 sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
290 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
291 sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
292 sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
293 sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
294 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
295 sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
296 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
299 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
301 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
302 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
304 /* Moving to the right sysclk and ES rev base */
305 ptr = ptr + (3 * clk_index) + sil_index;
307 /* MPU DPLL (unlocked already) */
309 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
310 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
312 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
313 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
315 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
316 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
318 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
319 sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
322 static void iva_init_34xx(u32 sil_index, u32 clk_index)
324 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
325 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
327 /* Moving to the right sysclk and ES rev base */
328 ptr = ptr + (3 * clk_index) + sil_index;
331 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
332 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
333 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
335 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
336 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
338 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
339 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
341 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
342 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
344 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
345 sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
347 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
348 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
350 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
354 * OMAP3630 specific functions
357 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
359 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
360 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
361 void (*f_lock_pll) (u32, u32, u32, u32);
362 int xip_safe, p0, p1, p2, p3;
364 xip_safe = is_running_in_sram();
366 /* Moving it to the right sysclk base */
372 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
373 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
374 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
377 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
378 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
380 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
381 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
383 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
384 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
386 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
387 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
389 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
390 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
393 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
395 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
397 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
399 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
401 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
403 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
404 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
405 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
407 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
409 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
411 } else if (is_running_in_flash()) {
413 * if running from flash, jump to small relocated code
416 f_lock_pll = (void *) (SRAM_CLK_CODE);
418 p0 = readl(&prcm_base->clken_pll);
419 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
420 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
421 sr32(&p0, 4, 4, ptr->fsel);
423 p1 = readl(&prcm_base->clksel1_pll);
424 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
425 sr32(&p1, 27, 5, ptr->m2);
426 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
427 sr32(&p1, 16, 11, ptr->m);
428 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
429 sr32(&p1, 8, 7, ptr->n);
430 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
433 p2 = readl(&prcm_base->clksel_core);
435 sr32(&p2, 8, 4, CORE_SSI_DIV);
437 sr32(&p2, 4, 2, CORE_FUSB_DIV);
439 sr32(&p2, 2, 2, CORE_L4_DIV);
441 sr32(&p2, 0, 2, CORE_L3_DIV);
443 p3 = (u32)&prcm_base->idlest_ckgen;
445 (*f_lock_pll) (p0, p1, p2, p3);
449 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
451 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
452 struct dpll_per_36x_param *ptr;
454 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
456 /* Moving it to the right sysclk base */
459 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
460 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
461 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
463 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
464 sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
466 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
467 sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
469 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
470 sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
472 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
473 sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
475 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
476 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
478 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
479 sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
481 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
482 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
484 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
485 sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
487 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
488 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
489 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
492 static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
494 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
495 dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
497 /* Moving it to the right sysclk base */
498 ptr = ptr + clk_index;
500 /* PER2 DPLL (DPLL5) */
501 sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
502 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
503 sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
504 sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
505 sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
506 sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
507 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
510 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
512 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
513 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
515 /* Moving to the right sysclk */
518 /* MPU DPLL (unlocked already */
520 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
521 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
523 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
524 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
526 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
527 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
530 static void iva_init_36xx(u32 sil_index, u32 clk_index)
532 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
533 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
535 /* Moving to the right sysclk */
539 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
540 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
541 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
543 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
544 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
546 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
547 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
549 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
550 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
552 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
553 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
555 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
558 /******************************************************************************
559 * prcm_init() - inits clocks for PRCM as defined in clocks.h
560 * called from SRAM, or Flash (using temp SRAM stack).
561 *****************************************************************************/
564 u32 osc_clk = 0, sys_clkin_sel;
565 u32 clk_index, sil_index = 0;
566 struct prm *prm_base = (struct prm *)PRM_BASE;
567 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
570 * Gauge the input clock speed and find out the sys_clkin_sel
571 * value corresponding to the input clock.
573 osc_clk = get_osc_clk_speed();
574 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
576 /* set input crystal speed */
577 sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
579 /* If the input clock is greater than 19.2M always divide/2 */
580 if (sys_clkin_sel > 2) {
581 /* input clock divider */
582 sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
583 clk_index = sys_clkin_sel / 2;
585 /* input clock divider */
586 sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
587 clk_index = sys_clkin_sel;
590 if (get_cpu_family() == CPU_OMAP36XX) {
592 * In warm reset conditions on OMAP36xx/AM/DM37xx
593 * the rom code incorrectly sets the DPLL4 clock
594 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
595 * the AM/DM37x TRM explains that the /6.5 divider
596 * is used only when the input clock is 13MHz.
598 * If the part is in this cpu family *and* the input
599 * clock *is not* 13 MHz, then reset the DPLL4 clock
600 * input divider to /1 as it should never set to /6.5
603 if (sys_clkin_sel != 1) /* 13 MHz */
604 /* Bit 8: DPLL4_CLKINP_DIV */
605 sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
607 /* Unlock MPU DPLL (slows things down, and needed later) */
608 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
609 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
612 dpll3_init_36xx(0, clk_index);
613 dpll4_init_36xx(0, clk_index);
614 dpll5_init_36xx(0, clk_index);
615 iva_init_36xx(0, clk_index);
616 mpu_init_36xx(0, clk_index);
618 /* Lock MPU DPLL to set frequency */
619 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
620 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
624 * The DPLL tables are defined according to sysclk value and
625 * silicon revision. The clk_index value will be used to get
626 * the values for that input sysclk from the DPLL param table
627 * and sil_index will get the values for that SysClk for the
628 * appropriate silicon rev.
630 if (((get_cpu_family() == CPU_OMAP34XX)
631 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
632 (get_cpu_family() == CPU_AM35XX))
635 /* Unlock MPU DPLL (slows things down, and needed later) */
636 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
637 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
640 dpll3_init_34xx(sil_index, clk_index);
641 dpll4_init_34xx(sil_index, clk_index);
642 dpll5_init_34xx(sil_index, clk_index);
643 if (get_cpu_family() != CPU_AM35XX)
644 iva_init_34xx(sil_index, clk_index);
646 mpu_init_34xx(sil_index, clk_index);
648 /* Lock MPU DPLL to set frequency */
649 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
650 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
654 /* Set up GPTimers to sys_clk source only */
655 sr32(&prcm_base->clksel_per, 0, 8, 0xff);
656 sr32(&prcm_base->clksel_wkup, 0, 1, 1);
662 * Enable usb ehci uhh, tll clocks
664 void ehci_clocks_enable(void)
666 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
668 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
669 sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
671 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
672 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
674 sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
675 /* Enable USBTTL_ICLK */
676 sr32(&prcm_base->iclken3_core, 2, 1, 1);
677 /* Enable USBTTL_FCLK */
678 sr32(&prcm_base->fclken3_core, 2, 1, 1);
681 /******************************************************************************
682 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
683 *****************************************************************************/
684 void per_clocks_enable(void)
686 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
688 /* Enable GP2 timer. */
689 sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
690 sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
691 sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
693 #ifdef CONFIG_SYS_NS16550
694 /* Enable UART1 clocks */
695 sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
696 sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
699 sr32(&prcm_base->fclken_per, 11, 1, 0x1);
700 sr32(&prcm_base->iclken_per, 11, 1, 0x1);
703 #ifdef CONFIG_OMAP3_GPIO_2
704 sr32(&prcm_base->fclken_per, 13, 1, 1);
705 sr32(&prcm_base->iclken_per, 13, 1, 1);
707 #ifdef CONFIG_OMAP3_GPIO_3
708 sr32(&prcm_base->fclken_per, 14, 1, 1);
709 sr32(&prcm_base->iclken_per, 14, 1, 1);
711 #ifdef CONFIG_OMAP3_GPIO_4
712 sr32(&prcm_base->fclken_per, 15, 1, 1);
713 sr32(&prcm_base->iclken_per, 15, 1, 1);
715 #ifdef CONFIG_OMAP3_GPIO_5
716 sr32(&prcm_base->fclken_per, 16, 1, 1);
717 sr32(&prcm_base->iclken_per, 16, 1, 1);
719 #ifdef CONFIG_OMAP3_GPIO_6
720 sr32(&prcm_base->fclken_per, 17, 1, 1);
721 sr32(&prcm_base->iclken_per, 17, 1, 1);
724 #ifdef CONFIG_SYS_I2C_OMAP34XX
725 /* Turn on all 3 I2C clocks */
726 sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
727 sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
729 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
730 sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
732 if (get_cpu_family() != CPU_AM35XX)
733 sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
735 sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
736 sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
737 sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
738 sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
739 sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
740 sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
741 sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
742 if (get_cpu_family() != CPU_AM35XX) {
743 sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
744 sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);