3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/clocks_omap3.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/sys_proto.h>
34 #include <environment.h>
37 /******************************************************************************
38 * get_sys_clk_speed() - determine reference oscillator speed
39 * based on known 32kHz clock and gptimer.
40 *****************************************************************************/
41 u32 get_osc_clk_speed(void)
43 u32 start, cstart, cend, cdiff, cdiv, val;
44 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
45 struct prm *prm_base = (struct prm *)PRM_BASE;
46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
47 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
49 val = readl(&prm_base->clksrc_ctrl);
51 if (val & SYSCLKDIV_2)
57 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
59 /* select sys_clk for GPT1 */
60 writel(val, &prcm_base->clksel_wkup);
62 /* Enable I and F Clocks for GPT1 */
63 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
64 writel(val, &prcm_base->iclken_wkup);
66 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
67 writel(val, &prcm_base->fclken_wkup);
69 writel(0, &gpt1_base->tldr); /* start counting at 0 */
70 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
72 /* enable 32kHz source, determine sys_clk via gauging */
74 /* start time in 20 cycles */
75 start = 20 + readl(&s32k_base->s32k_cr);
77 /* dead loop till start time */
78 while (readl(&s32k_base->s32k_cr) < start);
80 /* get start sys_clk count */
81 cstart = readl(&gpt1_base->tcrr);
83 /* wait for 40 cycles */
84 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
85 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
86 cdiff = cend - cstart; /* get elapsed ticks */
89 /* based on number of ticks assign speed */
92 else if (cdiff > 15200)
94 else if (cdiff > 13000)
96 else if (cdiff > 9000)
98 else if (cdiff > 7600)
104 /******************************************************************************
105 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
106 * input oscillator clock frequency.
107 *****************************************************************************/
108 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
130 * OMAP34XX/35XX specific functions
133 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
135 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
136 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
137 void (*f_lock_pll) (u32, u32, u32, u32);
138 int xip_safe, p0, p1, p2, p3;
140 xip_safe = is_running_in_sram();
142 /* Moving to the right sysclk and ES rev base */
143 ptr = ptr + (3 * clk_index) + sil_index;
148 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
150 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
151 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
155 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
156 * work. write another value and then default value.
159 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
160 sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
161 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
163 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
164 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
166 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
167 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
169 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
170 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
172 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
173 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
176 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
178 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
180 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
182 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
184 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
186 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
187 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
188 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
190 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
194 } else if (is_running_in_flash()) {
196 * if running from flash, jump to small relocated code
199 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
202 p0 = readl(&prcm_base->clken_pll);
203 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
204 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
205 sr32(&p0, 4, 4, ptr->fsel);
207 p1 = readl(&prcm_base->clksel1_pll);
208 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
209 sr32(&p1, 27, 5, ptr->m2);
210 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
211 sr32(&p1, 16, 11, ptr->m);
212 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
213 sr32(&p1, 8, 7, ptr->n);
214 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
217 p2 = readl(&prcm_base->clksel_core);
219 sr32(&p2, 8, 4, CORE_SSI_DIV);
221 sr32(&p2, 4, 2, CORE_FUSB_DIV);
223 sr32(&p2, 2, 2, CORE_L4_DIV);
225 sr32(&p2, 0, 2, CORE_L3_DIV);
227 p3 = (u32)&prcm_base->idlest_ckgen;
229 (*f_lock_pll) (p0, p1, p2, p3);
233 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
235 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
236 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
238 /* Moving it to the right sysclk base */
239 ptr = ptr + clk_index;
241 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
242 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
243 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
246 * Errata 1.50 Workaround for OMAP3 ES1.0 only
247 * If using default divisors, write default divisor + 1
248 * and then the actual divisor value
251 sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
252 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
254 sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
255 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
257 sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
258 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
260 sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
261 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
262 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
263 sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
264 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
267 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
268 sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
270 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
271 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
273 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
274 sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
276 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
277 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
278 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
281 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
283 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
284 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
286 /* Moving to the right sysclk and ES rev base */
287 ptr = ptr + (3 * clk_index) + sil_index;
289 /* MPU DPLL (unlocked already) */
291 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
292 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
294 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
295 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
297 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
298 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
300 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
301 sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
304 static void iva_init_34xx(u32 sil_index, u32 clk_index)
306 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
307 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
309 /* Moving to the right sysclk and ES rev base */
310 ptr = ptr + (3 * clk_index) + sil_index;
313 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
314 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
315 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
317 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
318 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
320 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
321 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
323 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
324 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
326 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
327 sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
329 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
330 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
332 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
336 * OMAP3630 specific functions
339 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
341 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
342 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
343 void (*f_lock_pll) (u32, u32, u32, u32);
344 int xip_safe, p0, p1, p2, p3;
346 xip_safe = is_running_in_sram();
348 /* Moving it to the right sysclk base */
354 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
355 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
356 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
359 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
360 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
362 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
363 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
365 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
366 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
368 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
369 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
371 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
372 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
375 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
377 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
379 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
381 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
383 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
385 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
386 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
387 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
389 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
391 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
393 } else if (is_running_in_flash()) {
395 * if running from flash, jump to small relocated code
398 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
401 p0 = readl(&prcm_base->clken_pll);
402 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
403 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
404 sr32(&p0, 4, 4, ptr->fsel);
406 p1 = readl(&prcm_base->clksel1_pll);
407 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
408 sr32(&p1, 27, 5, ptr->m2);
409 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
410 sr32(&p1, 16, 11, ptr->m);
411 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
412 sr32(&p1, 8, 7, ptr->n);
413 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
416 p2 = readl(&prcm_base->clksel_core);
418 sr32(&p2, 8, 4, CORE_SSI_DIV);
420 sr32(&p2, 4, 2, CORE_FUSB_DIV);
422 sr32(&p2, 2, 2, CORE_L4_DIV);
424 sr32(&p2, 0, 2, CORE_L3_DIV);
426 p3 = (u32)&prcm_base->idlest_ckgen;
428 (*f_lock_pll) (p0, p1, p2, p3);
432 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
434 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
435 struct dpll_per_36x_param *ptr;
437 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
439 /* Moving it to the right sysclk base */
442 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
443 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
444 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
446 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
447 sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
449 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
450 sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
452 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
453 sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
455 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
456 sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
458 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
459 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
461 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
462 sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
464 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
465 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
467 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
468 sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
470 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
471 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
472 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
475 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
477 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
478 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
480 /* Moving to the right sysclk */
483 /* MPU DPLL (unlocked already */
485 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
486 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
488 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
489 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
491 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
492 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
495 static void iva_init_36xx(u32 sil_index, u32 clk_index)
497 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
498 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
500 /* Moving to the right sysclk */
504 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
505 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
506 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
508 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
509 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
511 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
512 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
514 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
515 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
517 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
518 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
520 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
523 /******************************************************************************
524 * prcm_init() - inits clocks for PRCM as defined in clocks.h
525 * called from SRAM, or Flash (using temp SRAM stack).
526 *****************************************************************************/
529 u32 osc_clk = 0, sys_clkin_sel;
530 u32 clk_index, sil_index = 0;
531 struct prm *prm_base = (struct prm *)PRM_BASE;
532 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
535 * Gauge the input clock speed and find out the sys_clkin_sel
536 * value corresponding to the input clock.
538 osc_clk = get_osc_clk_speed();
539 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
541 /* set input crystal speed */
542 sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
544 /* If the input clock is greater than 19.2M always divide/2 */
545 if (sys_clkin_sel > 2) {
546 /* input clock divider */
547 sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
548 clk_index = sys_clkin_sel / 2;
550 /* input clock divider */
551 sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
552 clk_index = sys_clkin_sel;
555 if (get_cpu_family() == CPU_OMAP36XX) {
556 /* Unlock MPU DPLL (slows things down, and needed later) */
557 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
558 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
561 dpll3_init_36xx(0, clk_index);
562 dpll4_init_36xx(0, clk_index);
563 iva_init_36xx(0, clk_index);
564 mpu_init_36xx(0, clk_index);
566 /* Lock MPU DPLL to set frequency */
567 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
568 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
572 * The DPLL tables are defined according to sysclk value and
573 * silicon revision. The clk_index value will be used to get
574 * the values for that input sysclk from the DPLL param table
575 * and sil_index will get the values for that SysClk for the
576 * appropriate silicon rev.
578 if (((get_cpu_family() == CPU_OMAP34XX)
579 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
580 (get_cpu_family() == CPU_AM35XX))
583 /* Unlock MPU DPLL (slows things down, and needed later) */
584 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
585 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
588 dpll3_init_34xx(sil_index, clk_index);
589 dpll4_init_34xx(sil_index, clk_index);
590 iva_init_34xx(sil_index, clk_index);
591 mpu_init_34xx(sil_index, clk_index);
593 /* Lock MPU DPLL to set frequency */
594 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
595 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
599 /* Set up GPTimers to sys_clk source only */
600 sr32(&prcm_base->clksel_per, 0, 8, 0xff);
601 sr32(&prcm_base->clksel_wkup, 0, 1, 1);
606 /******************************************************************************
607 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
608 *****************************************************************************/
609 void per_clocks_enable(void)
611 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
613 /* Enable GP2 timer. */
614 sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
615 sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
616 sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
618 #ifdef CONFIG_SYS_NS16550
619 /* Enable UART1 clocks */
620 sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
621 sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
624 sr32(&prcm_base->fclken_per, 11, 1, 0x1);
625 sr32(&prcm_base->iclken_per, 11, 1, 0x1);
628 #ifdef CONFIG_OMAP3_GPIO_2
629 sr32(&prcm_base->fclken_per, 13, 1, 1);
630 sr32(&prcm_base->iclken_per, 13, 1, 1);
632 #ifdef CONFIG_OMAP3_GPIO_3
633 sr32(&prcm_base->fclken_per, 14, 1, 1);
634 sr32(&prcm_base->iclken_per, 14, 1, 1);
636 #ifdef CONFIG_OMAP3_GPIO_4
637 sr32(&prcm_base->fclken_per, 15, 1, 1);
638 sr32(&prcm_base->iclken_per, 15, 1, 1);
640 #ifdef CONFIG_OMAP3_GPIO_5
641 sr32(&prcm_base->fclken_per, 16, 1, 1);
642 sr32(&prcm_base->iclken_per, 16, 1, 1);
644 #ifdef CONFIG_OMAP3_GPIO_6
645 sr32(&prcm_base->fclken_per, 17, 1, 1);
646 sr32(&prcm_base->iclken_per, 17, 1, 1);
649 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
650 /* Turn on all 3 I2C clocks */
651 sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
652 sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
654 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
655 sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
657 sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
658 sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
659 sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
660 sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
661 sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
662 sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
663 sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
664 sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
665 sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
666 sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
667 sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
668 sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);