3 * Common functions for OMAP4/5 based boards
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
12 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/sys_proto.h>
17 #include <linux/sizes.h>
19 #include <asm/omap_common.h>
20 #include <linux/compiler.h>
21 #include <asm/cache.h>
22 #include <asm/system.h>
24 #define ARMV7_DCACHE_WRITEBACK 0xe
25 #define ARMV7_DOMAIN_CLIENT 1
26 #define ARMV7_DOMAIN_MASK (0x3 << 0)
28 DECLARE_GLOBAL_DATA_PTR;
30 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
33 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
35 for (i = 0; i < size; i++, pad++)
36 writew(pad->val, base + pad->offset);
39 static void set_mux_conf_regs(void)
41 switch (omap_hw_init_context()) {
42 case OMAP_INIT_CONTEXT_SPL:
43 set_muxconf_regs_essential();
45 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
47 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
48 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
49 set_muxconf_regs_essential();
59 /* Read Main ID Register (MIDR) */
60 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
65 static void omap_rev_string(void)
67 u32 omap_rev = omap_revision();
68 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
69 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
70 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
71 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
77 printf("%x ES%x.%x\n", omap_variant, major_rev,
81 #ifdef CONFIG_SPL_BUILD
82 void spl_display_print(void)
88 void __weak srcomp_enable(void)
92 #ifdef CONFIG_ARCH_CPU_INIT
94 * SOC specific cpu init
96 int arch_cpu_init(void)
98 save_omap_boot_params();
101 #endif /* CONFIG_ARCH_CPU_INIT */
105 * Description: Does early system init of watchdog, muxing, andclocks
106 * Watchdog disable is done always. For the rest what gets done
107 * depends on the boot mode in which this function is executed
108 * 1. s_init of SPL running from SRAM
109 * 2. s_init of U-Boot running from FLASH
110 * 3. s_init of U-Boot loaded to SDRAM by SPL
111 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
112 * Configuration Header feature
113 * Please have a look at the respective functions to see what gets
114 * done in each of these cases
115 * This function is called with SRAM stack.
120 * Save the boot parameters passed from romcode.
121 * We cannot delay the saving further than this,
122 * to prevent overwrites.
124 #ifdef CONFIG_SPL_BUILD
125 save_omap_boot_params();
127 init_omap_revision();
130 #ifdef CONFIG_SPL_BUILD
131 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
132 force_emif_self_refresh();
136 #ifdef CONFIG_SPL_BUILD
138 setup_clocks_for_console();
142 preloader_console_init();
146 #ifdef CONFIG_SPL_BUILD
147 /* For regular u-boot sdram_init() is called from dram_init() */
153 * Routine: wait_for_command_complete
154 * Description: Wait for posting to finish on watchdog
156 void wait_for_command_complete(struct watchdog *wd_base)
160 pending = readl(&wd_base->wwps);
165 * Routine: watchdog_init
166 * Description: Shut down watch dogs
168 void watchdog_init(void)
170 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
172 writel(WD_UNLOCK1, &wd2_base->wspr);
173 wait_for_command_complete(wd2_base);
174 writel(WD_UNLOCK2, &wd2_base->wspr);
179 * This function finds the SDRAM size available in the system
180 * based on DMM section configurations
181 * This is needed because the size of memory installed may be
182 * different on different versions of the board
184 u32 omap_sdram_size(void)
186 u32 section, i, valid;
187 u64 sdram_start = 0, sdram_end = 0, addr,
188 size, total_size = 0, trap_size = 0;
190 for (i = 0; i < 4; i++) {
191 section = __raw_readl(DMM_BASE + i*4);
192 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
193 (EMIF_SDRC_ADDRSPC_SHIFT);
194 addr = section & EMIF_SYS_ADDR_MASK;
196 /* See if the address is valid */
197 if ((addr >= DRAM_ADDR_SPACE_START) &&
198 (addr < DRAM_ADDR_SPACE_END)) {
199 size = ((section & EMIF_SYS_SIZE_MASK) >>
200 EMIF_SYS_SIZE_SHIFT);
204 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
205 if (!sdram_start || (addr < sdram_start))
207 if (!sdram_end || ((addr + size) > sdram_end))
208 sdram_end = addr + size;
216 total_size = (sdram_end - sdram_start) - (trap_size);
224 * Description: sets uboots idea of sdram size
229 gd->ram_size = omap_sdram_size();
234 * Print board information
238 puts(sysinfo.board_string);
243 * get_device_type(): tell if GP/HS/EMU/TST
245 u32 get_device_type(void)
247 return (readl((*ctrl)->control_status) &
248 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
251 #if defined(CONFIG_DISPLAY_CPUINFO)
253 * Print CPU information
255 int print_cpuinfo(void)
264 #ifndef CONFIG_SYS_DCACHE_OFF
265 void enable_caches(void)
267 /* Enable D-cache. I-cache is already enabled in start.S */
271 void dram_bank_mmu_setup(int bank)
276 u32 start = bd->bi_dram[bank].start >> 20;
277 u32 size = bd->bi_dram[bank].size >> 20;
278 u32 end = start + size;
280 debug("%s: bank: %d\n", __func__, bank);
281 for (i = start; i < end; i++)
282 set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
286 void arm_init_domains(void)
292 * Set DOMAIN to client access so that all permissions
293 * set in pagetables are validated by the mmu.
295 reg &= ~ARMV7_DOMAIN_MASK;
296 reg |= ARMV7_DOMAIN_CLIENT;