5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
34 #include <linux/compiler.h>
36 static int emif1_enabled = -1, emif2_enabled = -1;
38 void set_lpmode_selfrefresh(u32 base)
40 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
43 reg = readl(&emif->emif_pwr_mgmt_ctrl);
44 reg &= ~EMIF_REG_LP_MODE_MASK;
45 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
46 reg &= ~EMIF_REG_SR_TIM_MASK;
47 writel(reg, &emif->emif_pwr_mgmt_ctrl);
49 /* dummy read for the new SR_TIM to be loaded */
50 readl(&emif->emif_pwr_mgmt_ctrl);
53 void force_emif_self_refresh()
55 set_lpmode_selfrefresh(EMIF1_BASE);
56 set_lpmode_selfrefresh(EMIF2_BASE);
59 inline u32 emif_num(u32 base)
61 if (base == EMIF1_BASE)
63 else if (base == EMIF2_BASE)
70 * Get SDRAM type connected to EMIF.
71 * Assuming similar SDRAM parts are connected to both EMIF's
72 * which is typically the case. So it is sufficient to get
73 * SDRAM type from EMIF1.
77 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
79 return (readl(&emif->emif_sdram_config) &
80 EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
83 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
86 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
88 mr_addr |= cs << EMIF_REG_CS_SHIFT;
89 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
90 if (omap_revision() == OMAP4430_ES2_0)
91 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
93 mr = readl(&emif->emif_lpddr2_mode_reg_data);
94 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
96 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
97 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
98 ((mr & 0xff000000) >> 24) == (mr & 0xff))
104 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
106 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
108 mr_addr |= cs << EMIF_REG_CS_SHIFT;
109 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
110 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
113 void emif_reset_phy(u32 base)
115 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
118 iodft = readl(&emif->emif_iodft_tlgc);
119 iodft |= EMIF_REG_RESET_PHY_MASK;
120 writel(iodft, &emif->emif_iodft_tlgc);
123 static void do_lpddr2_init(u32 base, u32 cs)
126 const struct lpddr2_mr_regs *mr_regs;
128 get_lpddr2_mr_regs(&mr_regs);
129 /* Wait till device auto initialization is complete */
130 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
132 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
135 * Enough loops assuming a maximum of 2GHz
140 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
141 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
144 * Enable refresh along with writing MR2
145 * Encoding of RL in MR2 is (RL - 2)
147 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
148 set_mr(base, cs, mr_addr, mr_regs->mr2);
150 if (mr_regs->mr3 > 0)
151 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
154 static void lpddr2_init(u32 base, const struct emif_regs *regs)
156 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
159 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
162 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
163 * when EMIF_SDRAM_CONFIG register is written
165 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
168 * Set the SDRAM_CONFIG and PHY_CTRL for the
169 * un-locked frequency & default RL
171 writel(regs->sdram_config_init, &emif->emif_sdram_config);
172 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
174 do_ext_phy_settings(base, regs);
176 do_lpddr2_init(base, CS0);
177 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
178 do_lpddr2_init(base, CS1);
180 writel(regs->sdram_config, &emif->emif_sdram_config);
181 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
183 /* Enable refresh now */
184 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
188 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
192 void emif_update_timings(u32 base, const struct emif_regs *regs)
194 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
196 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
197 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
198 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
199 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
200 if (omap_revision() == OMAP4430_ES1_0) {
201 /* ES1 bug EMIF should be in force idle during freq_update */
202 writel(0, &emif->emif_pwr_mgmt_ctrl);
204 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
205 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
207 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
208 writel(regs->zq_config, &emif->emif_zq_config);
209 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
210 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
212 if ((omap_revision() >= OMAP5430_ES1_0) ||
213 (omap_revision() == DRA752_ES1_0)) {
214 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
215 &emif->emif_l3_config);
216 } else if (omap_revision() >= OMAP4460_ES1_0) {
217 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
218 &emif->emif_l3_config);
220 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
221 &emif->emif_l3_config);
225 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
227 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
229 /* keep sdram in self-refresh */
230 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
231 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
235 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
236 * Invert clock adds an additional half cycle delay on the command
237 * interface. The additional half cycle, is usually meant to enable
238 * leveling in the situation that DQS is later than CK on the board.It
239 * also helps provide some additional margin for leveling.
241 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
242 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
245 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
246 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
248 /* Launch Full leveling */
249 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
251 /* Wait till full leveling is complete */
252 readl(&emif->emif_rd_wr_lvl_ctl);
255 /* Read data eye leveling no of samples */
256 config_data_eye_leveling_samples(base);
258 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
259 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
262 /* Launch Incremental leveling */
263 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
267 static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
269 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
271 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
272 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
273 config_data_eye_leveling_samples(base);
275 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
276 writel(regs->sdram_config, &emif->emif_sdram_config);
279 static void ddr3_init(u32 base, const struct emif_regs *regs)
281 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
284 * Set SDRAM_CONFIG and PHY control registers to locked frequency
285 * and RL =7. As the default values of the Mode Registers are not
286 * defined, contents of mode Registers must be fully initialized.
287 * H/W takes care of this initialization
289 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
290 writel(regs->sdram_config_init, &emif->emif_sdram_config);
292 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
294 /* Update timing registers */
295 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
296 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
297 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
299 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
300 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
302 do_ext_phy_settings(base, regs);
304 /* enable leveling */
305 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
307 if (omap_revision() == DRA752_ES1_0)
308 ddr3_sw_leveling(base, regs);
310 ddr3_leveling(base, regs);
313 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
314 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
317 * Organization and refresh requirements for LPDDR2 devices of different
318 * types and densities. Derived from JESD209-2 section 2.4
320 const struct lpddr2_addressing addressing_table[] = {
321 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
322 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
323 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
324 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
325 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
326 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
327 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
328 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
329 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
330 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
331 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
334 static const u32 lpddr2_density_2_size_in_mbytes[] = {
348 * Calculate the period of DDR clock from frequency value and set the
349 * denominator and numerator in global variables for easy access later
351 static void set_ddr_clk_period(u32 freq)
355 * period_in_ns = 10^9/freq
359 cancel_out(T_num, T_den, 200);
364 * Convert time in nano seconds to number of cycles of DDR clock
366 static inline u32 ns_2_cycles(u32 ns)
368 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
372 * ns_2_cycles with the difference that the time passed is 2 times the actual
373 * value(to avoid fractions). The cycles returned is for the original value of
374 * the timing parameter
376 static inline u32 ns_x2_2_cycles(u32 ns)
378 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
382 * Find addressing table index based on the device's type(S2 or S4) and
385 s8 addressing_table_index(u8 type, u8 density, u8 width)
388 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
392 * Look at the way ADDR_TABLE_INDEX* values have been defined
393 * in emif.h compared to LPDDR2_DENSITY_* values
394 * The table is layed out in the increasing order of density
395 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
398 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
399 index = ADDR_TABLE_INDEX1GS2;
400 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
401 index = ADDR_TABLE_INDEX2GS2;
405 debug("emif: addressing table index %d\n", index);
411 * Find the the right timing table from the array of timing
412 * tables of the device using DDR clock frequency
414 static const struct lpddr2_ac_timings *get_timings_table(const struct
415 lpddr2_ac_timings const *const *device_timings,
418 u32 i, temp, freq_nearest;
419 const struct lpddr2_ac_timings *timings = 0;
421 emif_assert(freq <= MAX_LPDDR2_FREQ);
422 emif_assert(device_timings);
425 * Start with the maximum allowed frequency - that is always safe
427 freq_nearest = MAX_LPDDR2_FREQ;
429 * Find the timings table that has the max frequency value:
430 * i. Above or equal to the DDR frequency - safe
431 * ii. The lowest that satisfies condition (i) - optimal
433 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
434 temp = device_timings[i]->max_freq;
435 if ((temp >= freq) && (temp <= freq_nearest)) {
437 timings = device_timings[i];
440 debug("emif: timings table: %d\n", freq_nearest);
445 * Finds the value of emif_sdram_config_reg
446 * All parameters are programmed based on the device on CS0.
447 * If there is a device on CS1, it will be same as that on CS0 or
448 * it will be NVM. We don't support NVM yet.
449 * If cs1_device pointer is NULL it is assumed that there is no device
452 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
453 const struct lpddr2_device_details *cs1_device,
454 const struct lpddr2_addressing *addressing,
459 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
460 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
461 EMIF_REG_IBANK_POS_SHIFT;
463 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
465 config_reg |= RL << EMIF_REG_CL_SHIFT;
467 config_reg |= addressing->row_sz[cs0_device->io_width] <<
468 EMIF_REG_ROWSIZE_SHIFT;
470 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
472 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
473 EMIF_REG_EBANK_SHIFT;
475 config_reg |= addressing->col_sz[cs0_device->io_width] <<
476 EMIF_REG_PAGESIZE_SHIFT;
481 static u32 get_sdram_ref_ctrl(u32 freq,
482 const struct lpddr2_addressing *addressing)
484 u32 ref_ctrl = 0, val = 0, freq_khz;
485 freq_khz = freq / 1000;
487 * refresh rate to be set is 'tREFI * freq in MHz
488 * division by 10000 to account for khz and x10 in t_REFI_us_x10
490 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
491 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
496 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
497 const struct lpddr2_min_tck *min_tck,
498 const struct lpddr2_addressing *addressing)
500 u32 tim1 = 0, val = 0;
501 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
502 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
504 if (addressing->num_banks == BANKS8)
505 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
508 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
510 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
512 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
513 tim1 |= val << EMIF_REG_T_RC_SHIFT;
515 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
516 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
518 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
519 tim1 |= val << EMIF_REG_T_WR_SHIFT;
521 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
522 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
524 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
525 tim1 |= val << EMIF_REG_T_RP_SHIFT;
530 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
531 const struct lpddr2_min_tck *min_tck)
533 u32 tim2 = 0, val = 0;
534 val = max(min_tck->tCKE, timings->tCKE) - 1;
535 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
537 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
538 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
541 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
544 val = ns_2_cycles(timings->tXSR) - 1;
545 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
546 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
548 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
549 tim2 |= val << EMIF_REG_T_XP_SHIFT;
554 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
555 const struct lpddr2_min_tck *min_tck,
556 const struct lpddr2_addressing *addressing)
558 u32 tim3 = 0, val = 0;
559 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
560 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
562 val = ns_2_cycles(timings->tRFCab) - 1;
563 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
565 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
566 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
568 val = ns_2_cycles(timings->tZQCS) - 1;
569 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
571 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
572 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
577 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
578 const struct lpddr2_addressing *addressing,
584 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
585 addressing->t_REFI_us_x10;
588 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
589 addressing->t_REFI_us_x10;
590 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
592 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
594 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
596 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
599 * Assuming that two chipselects have a single calibration resistor
600 * If there are indeed two calibration resistors, then this flag should
601 * be enabled to take advantage of dual calibration feature.
602 * This data should ideally come from board files. But considering
603 * that none of the boards today have calibration resistors per CS,
604 * it would be an unnecessary overhead.
606 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
608 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
610 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
615 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
616 const struct lpddr2_addressing *addressing,
619 u32 alert = 0, interval;
621 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
624 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
626 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
628 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
630 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
632 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
634 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
639 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
641 u32 idle = 0, val = 0;
643 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
645 /*Maximum value in normal conditions - suggested by hw team */
647 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
649 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
654 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
656 u32 phy = 0, val = 0;
658 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
660 if (freq <= 100000000)
661 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
662 else if (freq <= 200000000)
663 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
665 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
666 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
668 /* Other fields are constant magic values. Hardcode them together */
669 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
670 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
675 static u32 get_emif_mem_size(u32 base)
677 u32 size_mbytes = 0, temp;
678 struct emif_device_details dev_details;
679 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
680 u32 emif_nr = emif_num(base);
682 emif_reset_phy(base);
683 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
685 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
687 emif_reset_phy(base);
689 if (dev_details.cs0_device_details) {
690 temp = dev_details.cs0_device_details->density;
691 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
694 if (dev_details.cs1_device_details) {
695 temp = dev_details.cs1_device_details->density;
696 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
698 /* convert to bytes */
699 return size_mbytes << 20;
702 /* Gets the encoding corresponding to a given DMM section size */
703 u32 get_dmm_section_size_map(u32 section_size)
706 * Section size mapping:
707 * 0x0: 16-MiB section
708 * 0x1: 32-MiB section
709 * 0x2: 64-MiB section
710 * 0x3: 128-MiB section
711 * 0x4: 256-MiB section
712 * 0x5: 512-MiB section
716 section_size >>= 24; /* divide by 16 MB */
717 return log_2_n_round_down(section_size);
720 static void emif_calculate_regs(
721 const struct emif_device_details *emif_dev_details,
722 u32 freq, struct emif_regs *regs)
725 const struct lpddr2_addressing *addressing;
726 const struct lpddr2_ac_timings *timings;
727 const struct lpddr2_min_tck *min_tck;
728 const struct lpddr2_device_details *cs0_dev_details =
729 emif_dev_details->cs0_device_details;
730 const struct lpddr2_device_details *cs1_dev_details =
731 emif_dev_details->cs1_device_details;
732 const struct lpddr2_device_timings *cs0_dev_timings =
733 emif_dev_details->cs0_device_timings;
735 emif_assert(emif_dev_details);
738 * You can not have a device on CS1 without one on CS0
739 * So configuring EMIF without a device on CS0 doesn't
742 emif_assert(cs0_dev_details);
743 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
745 * If there is a device on CS1 it should be same type as CS0
746 * (or NVM. But NVM is not supported in this driver yet)
748 emif_assert((cs1_dev_details == NULL) ||
749 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
750 (cs0_dev_details->type == cs1_dev_details->type));
751 emif_assert(freq <= MAX_LPDDR2_FREQ);
753 set_ddr_clk_period(freq);
756 * The device on CS0 is used for all timing calculations
757 * There is only one set of registers for timings per EMIF. So, if the
758 * second CS(CS1) has a device, it should have the same timings as the
761 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
762 emif_assert(timings);
763 min_tck = cs0_dev_timings->min_tck;
765 temp = addressing_table_index(cs0_dev_details->type,
766 cs0_dev_details->density,
767 cs0_dev_details->io_width);
769 emif_assert((temp >= 0));
770 addressing = &(addressing_table[temp]);
771 emif_assert(addressing);
773 sys_freq = get_sys_clk_freq();
775 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
777 addressing, RL_BOOT);
779 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
781 addressing, RL_FINAL);
783 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
785 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
787 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
789 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
791 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
793 regs->temp_alert_config =
794 get_temp_alert_config(cs1_dev_details, addressing, 0);
796 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
797 LPDDR2_VOLTAGE_STABLE);
799 regs->emif_ddr_phy_ctlr_1_init =
800 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
802 regs->emif_ddr_phy_ctlr_1 =
803 get_ddr_phy_ctrl_1(freq, RL_FINAL);
807 print_timing_reg(regs->sdram_config_init);
808 print_timing_reg(regs->sdram_config);
809 print_timing_reg(regs->ref_ctrl);
810 print_timing_reg(regs->sdram_tim1);
811 print_timing_reg(regs->sdram_tim2);
812 print_timing_reg(regs->sdram_tim3);
813 print_timing_reg(regs->read_idle_ctrl);
814 print_timing_reg(regs->temp_alert_config);
815 print_timing_reg(regs->zq_config);
816 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
817 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
819 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
821 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
822 const char *get_lpddr2_type(u8 type_id)
834 const char *get_lpddr2_io_width(u8 width_id)
837 case LPDDR2_IO_WIDTH_8:
839 case LPDDR2_IO_WIDTH_16:
841 case LPDDR2_IO_WIDTH_32:
848 const char *get_lpddr2_manufacturer(u32 manufacturer)
850 switch (manufacturer) {
851 case LPDDR2_MANUFACTURER_SAMSUNG:
853 case LPDDR2_MANUFACTURER_QIMONDA:
855 case LPDDR2_MANUFACTURER_ELPIDA:
857 case LPDDR2_MANUFACTURER_ETRON:
859 case LPDDR2_MANUFACTURER_NANYA:
861 case LPDDR2_MANUFACTURER_HYNIX:
863 case LPDDR2_MANUFACTURER_MOSEL:
865 case LPDDR2_MANUFACTURER_WINBOND:
867 case LPDDR2_MANUFACTURER_ESMT:
869 case LPDDR2_MANUFACTURER_SPANSION:
871 case LPDDR2_MANUFACTURER_SST:
873 case LPDDR2_MANUFACTURER_ZMOS:
875 case LPDDR2_MANUFACTURER_INTEL:
877 case LPDDR2_MANUFACTURER_NUMONYX:
879 case LPDDR2_MANUFACTURER_MICRON:
886 static void display_sdram_details(u32 emif_nr, u32 cs,
887 struct lpddr2_device_details *device)
890 const char *type_str;
891 char density_str[10];
894 debug("EMIF%d CS%d\t", emif_nr, cs);
901 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
902 type_str = get_lpddr2_type(device->type);
904 density = lpddr2_density_2_size_in_mbytes[device->density];
905 if ((density / 1024 * 1024) == density) {
907 sprintf(density_str, "%d GB", density);
909 sprintf(density_str, "%d MB", density);
910 if (mfg_str && type_str)
911 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
914 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
915 struct lpddr2_device_details *lpddr2_device)
919 mr = get_mr(base, cs, LPDDR2_MR0);
921 /* Mode register value bigger than 8 bit */
925 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
930 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
933 /* DNV supported - But DNV is only supported for NVM */
937 mr = get_mr(base, cs, LPDDR2_MR4);
939 /* Mode register value bigger than 8 bit */
943 mr = get_mr(base, cs, LPDDR2_MR5);
945 /* Mode register value bigger than 8 bit */
949 if (!get_lpddr2_manufacturer(mr)) {
950 /* Manufacturer not identified */
953 lpddr2_device->manufacturer = mr;
955 mr = get_mr(base, cs, LPDDR2_MR6);
957 /* Mode register value bigger than 8 bit */
961 mr = get_mr(base, cs, LPDDR2_MR7);
963 /* Mode register value bigger than 8 bit */
967 mr = get_mr(base, cs, LPDDR2_MR8);
969 /* Mode register value bigger than 8 bit */
973 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
974 if (!get_lpddr2_type(temp)) {
978 lpddr2_device->type = temp;
980 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
981 if (temp > LPDDR2_DENSITY_32Gb) {
982 /* Density not supported */
985 lpddr2_device->density = temp;
987 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
988 if (!get_lpddr2_io_width(temp)) {
989 /* IO width unsupported value */
992 lpddr2_device->io_width = temp;
995 * If all the above tests pass we should
996 * have a device on this chip-select
1001 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1002 struct lpddr2_device_details *lpddr2_dev_details)
1005 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1007 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1009 if (!lpddr2_dev_details)
1012 /* Do the minimum init for mode register accesses */
1013 if (!(running_from_sdram() || warm_reset())) {
1014 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1015 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1018 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1021 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1023 return lpddr2_dev_details;
1025 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1027 static void do_sdram_init(u32 base)
1029 const struct emif_regs *regs;
1030 u32 in_sdram, emif_nr;
1032 debug(">>do_sdram_init() %x\n", base);
1034 in_sdram = running_from_sdram();
1035 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1037 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1038 emif_get_reg_dump(emif_nr, ®s);
1040 debug("EMIF: reg dump not provided\n");
1045 * The user has not provided the register values. We need to
1046 * calculate it based on the timings and the DDR frequency
1048 struct emif_device_details dev_details;
1049 struct emif_regs calculated_regs;
1052 * Get device details:
1053 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1054 * - Obtained from user otherwise
1056 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1057 emif_reset_phy(base);
1058 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1060 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1062 emif_reset_phy(base);
1064 /* Return if no devices on this EMIF */
1065 if (!dev_details.cs0_device_details &&
1066 !dev_details.cs1_device_details) {
1071 * Get device timings:
1072 * - Default timings specified by JESD209-2 if
1073 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1074 * - Obtained from user otherwise
1076 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1077 &dev_details.cs1_device_timings);
1079 /* Calculate the register values */
1080 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1081 regs = &calculated_regs;
1082 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1085 * Initializing the LPDDR2 device can not happen from SDRAM.
1086 * Changing the timing registers in EMIF can happen(going from one
1089 if (!(in_sdram || warm_reset())) {
1090 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1091 lpddr2_init(base, regs);
1093 ddr3_init(base, regs);
1095 if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1096 set_lpmode_selfrefresh(base);
1097 emif_reset_phy(base);
1098 if (omap_revision() == DRA752_ES1_0)
1099 ddr3_sw_leveling(base, regs);
1101 ddr3_leveling(base, regs);
1104 /* Write to the shadow registers */
1105 emif_update_timings(base, regs);
1107 debug("<<do_sdram_init() %x\n", base);
1110 void emif_post_init_config(u32 base)
1112 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1113 u32 omap_rev = omap_revision();
1115 /* reset phy on ES2.0 */
1116 if (omap_rev == OMAP4430_ES2_0)
1117 emif_reset_phy(base);
1119 /* Put EMIF back in smart idle on ES1.0 */
1120 if (omap_rev == OMAP4430_ES1_0)
1121 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1124 void dmm_init(u32 base)
1126 const struct dmm_lisa_map_regs *lisa_map_regs;
1127 u32 i, section, valid;
1129 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1130 emif_get_dmm_regs(&lisa_map_regs);
1132 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1133 u32 section_cnt, sys_addr;
1134 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1138 sys_addr = CONFIG_SYS_SDRAM_BASE;
1139 emif1_size = get_emif_mem_size(EMIF1_BASE);
1140 emif2_size = get_emif_mem_size(EMIF2_BASE);
1141 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1143 if (!emif1_size && !emif2_size)
1146 /* symmetric interleaved section */
1147 if (emif1_size && emif2_size) {
1148 mapped_size = min(emif1_size, emif2_size);
1149 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1150 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1152 section_map |= (sys_addr >> 24) <<
1153 EMIF_SYS_ADDR_SHIFT;
1154 section_map |= get_dmm_section_size_map(mapped_size * 2)
1155 << EMIF_SYS_SIZE_SHIFT;
1156 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1157 emif1_size -= mapped_size;
1158 emif2_size -= mapped_size;
1159 sys_addr += (mapped_size * 2);
1164 * Single EMIF section(we can have a maximum of 1 single EMIF
1165 * section- either EMIF1 or EMIF2 or none, but not both)
1168 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1169 section_map |= get_dmm_section_size_map(emif1_size)
1170 << EMIF_SYS_SIZE_SHIFT;
1172 section_map |= (mapped_size >> 24) <<
1173 EMIF_SDRC_ADDR_SHIFT;
1175 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1179 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1180 section_map |= get_dmm_section_size_map(emif2_size) <<
1181 EMIF_SYS_SIZE_SHIFT;
1183 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1185 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1189 if (section_cnt == 2) {
1190 /* Only 1 section - either symmetric or single EMIF */
1191 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1192 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1193 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1195 /* 2 sections - 1 symmetric, 1 single EMIF */
1196 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1197 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1200 /* TRAP for invalid TILER mappings in section 0 */
1201 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1203 if (omap_revision() >= OMAP4460_ES1_0)
1204 lis_map_regs_calculated.is_ma_present = 1;
1206 lisa_map_regs = &lis_map_regs_calculated;
1208 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1209 (struct dmm_lisa_map_regs *)base;
1211 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1212 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1213 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1214 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1216 writel(lisa_map_regs->dmm_lisa_map_3,
1217 &hw_lisa_map_regs->dmm_lisa_map_3);
1218 writel(lisa_map_regs->dmm_lisa_map_2,
1219 &hw_lisa_map_regs->dmm_lisa_map_2);
1220 writel(lisa_map_regs->dmm_lisa_map_1,
1221 &hw_lisa_map_regs->dmm_lisa_map_1);
1222 writel(lisa_map_regs->dmm_lisa_map_0,
1223 &hw_lisa_map_regs->dmm_lisa_map_0);
1225 if (lisa_map_regs->is_ma_present) {
1227 (struct dmm_lisa_map_regs *)MA_BASE;
1229 writel(lisa_map_regs->dmm_lisa_map_3,
1230 &hw_lisa_map_regs->dmm_lisa_map_3);
1231 writel(lisa_map_regs->dmm_lisa_map_2,
1232 &hw_lisa_map_regs->dmm_lisa_map_2);
1233 writel(lisa_map_regs->dmm_lisa_map_1,
1234 &hw_lisa_map_regs->dmm_lisa_map_1);
1235 writel(lisa_map_regs->dmm_lisa_map_0,
1236 &hw_lisa_map_regs->dmm_lisa_map_0);
1240 * EMIF should be configured only when
1241 * memory is mapped on it. Using emif1_enabled
1242 * and emif2_enabled variables for this.
1246 for (i = 0; i < 4; i++) {
1247 section = __raw_readl(DMM_BASE + i*4);
1248 valid = (section & EMIF_SDRC_MAP_MASK) >>
1249 (EMIF_SDRC_MAP_SHIFT);
1254 } else if (valid == 1) {
1256 } else if (valid == 2) {
1264 * SDRAM initialization:
1265 * SDRAM initialization has two parts:
1266 * 1. Configuring the SDRAM device
1267 * 2. Update the AC timings related parameters in the EMIF module
1268 * (1) should be done only once and should not be done while we are
1269 * running from SDRAM.
1270 * (2) can and should be done more than once if OPP changes.
1271 * Particularly, this may be needed when we boot without SPL and
1272 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1273 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1274 * the frequency. So,
1275 * Doing (1) and (2) makes sense - first time initialization
1276 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1277 * Doing (1) and not (2) doen't make sense
1278 * See do_sdram_init() for the details
1280 void sdram_init(void)
1282 u32 in_sdram, size_prog, size_detect;
1283 u32 sdram_type = emif_sdram_type();
1285 debug(">>sdram_init()\n");
1287 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1290 in_sdram = running_from_sdram();
1291 debug("in_sdram = %d\n", in_sdram);
1294 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1295 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1296 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1297 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1304 do_sdram_init(EMIF1_BASE);
1307 do_sdram_init(EMIF2_BASE);
1309 if (!(in_sdram || warm_reset())) {
1311 emif_post_init_config(EMIF1_BASE);
1313 emif_post_init_config(EMIF2_BASE);
1316 /* for the shadow registers to take effect */
1317 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1320 /* Do some testing after the init */
1322 size_prog = omap_sdram_size();
1323 size_prog = log_2_n_round_down(size_prog);
1324 size_prog = (1 << size_prog);
1326 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1328 /* Compare with the size programmed */
1329 if (size_detect != size_prog) {
1330 printf("SDRAM: identified size not same as expected"
1331 " size identified: %x expected: %x\n",
1335 debug("get_ram_size() successful");
1338 debug("<<sdram_init()\n");