3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
42 * printing to console doesn't work unless
43 * this code is executed from SPL
45 #define printf(fmt, args...)
49 static inline u32 __get_sys_clk_index(void)
53 * For ES1 the ROM code calibration of sys clock is not reliable
54 * due to hw issue. So, use hard-coded value. If this value is not
55 * correct for any board over-ride this function in board file
56 * From ES2.0 onwards you will get this information from
59 if (omap_revision() == OMAP4430_ES1_0)
60 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
62 /* SYS_CLKSEL - 1 to match the dpll param array indices */
63 ind = (readl(&prcm->cm_sys_clksel) &
64 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
69 u32 get_sys_clk_index(void)
70 __attribute__ ((weak, alias("__get_sys_clk_index")));
72 u32 get_sys_clk_freq(void)
74 u8 index = get_sys_clk_index();
75 return sys_clk_array[index];
78 static inline void do_bypass_dpll(u32 *const base)
80 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
82 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
83 CM_CLKMODE_DPLL_DPLL_EN_MASK,
84 DPLL_EN_FAST_RELOCK_BYPASS <<
85 CM_CLKMODE_DPLL_EN_SHIFT);
88 static inline void wait_for_bypass(u32 *const base)
90 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
92 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
94 printf("Bypassing DPLL failed %p\n", base);
98 static inline void do_lock_dpll(u32 *const base)
100 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
102 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
103 CM_CLKMODE_DPLL_DPLL_EN_MASK,
104 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
107 static inline void wait_for_lock(u32 *const base)
109 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
111 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
112 &dpll_regs->cm_idlest_dpll, LDELAY)) {
113 printf("DPLL locking failed for %p\n", base);
118 static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
122 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
127 temp = readl(&dpll_regs->cm_clksel_dpll);
129 temp &= ~CM_CLKSEL_DPLL_M_MASK;
130 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
132 temp &= ~CM_CLKSEL_DPLL_N_MASK;
133 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
135 writel(temp, &dpll_regs->cm_clksel_dpll);
141 setup_post_dividers(base, params);
143 /* Wait till the DPLL locks */
148 u32 omap_ddr_clk(void)
150 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
151 const struct dpll_params *core_dpll_params;
153 omap_rev = omap_revision();
154 sys_clk_khz = get_sys_clk_freq() / 1000;
156 core_dpll_params = get_core_dpll_params();
158 debug("sys_clk %d\n ", sys_clk_khz * 1000);
160 /* Find Core DPLL locked frequency first */
161 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
162 (core_dpll_params->n + 1);
164 if (omap_rev < OMAP5430_ES1_0) {
166 * DDR frequency is PHY_ROOT_CLK/2
167 * PHY_ROOT_CLK = Fdpll/2/M2
172 * DDR frequency is PHY_ROOT_CLK
173 * PHY_ROOT_CLK = Fdpll/2/M2
178 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
179 ddr_clk *= 1000; /* convert to Hz */
180 debug("ddr_clk %d\n ", ddr_clk);
188 * Resulting MPU frequencies:
189 * 4430 ES1.0 : 600 MHz
190 * 4430 ES2.x : 792 MHz (OPP Turbo)
191 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
193 void configure_mpu_dpll(void)
195 const struct dpll_params *params;
196 struct dpll_regs *mpu_dpll_regs;
198 omap_rev = omap_revision();
201 * DCC and clock divider settings for 4460.
202 * DCC is required, if more than a certain frequency is required.
206 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
208 (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
209 bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
210 clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
211 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
212 setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
213 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
214 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
215 CM_CLKSEL_DCC_EN_MASK);
218 params = get_mpu_dpll_params();
219 do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
220 debug("MPU DPLL locked\n");
223 static void setup_dplls(void)
225 u32 sysclk_ind, temp;
226 const struct dpll_params *params;
227 debug("setup_dplls\n");
229 sysclk_ind = get_sys_clk_index();
232 params = get_core_dpll_params(); /* default - safest */
234 * Do not lock the core DPLL now. Just set it up.
235 * Core DPLL will be locked after setting up EMIF
236 * using the FREQ_UPDATE method(freq_update_core())
238 do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK);
239 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
240 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
241 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
242 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
243 writel(temp, &prcm->cm_clksel_core);
244 debug("Core DPLL configured\n");
247 params = get_per_dpll_params();
248 do_setup_dpll(&prcm->cm_clkmode_dpll_per,
250 debug("PER DPLL locked\n");
253 configure_mpu_dpll();
256 static void setup_non_essential_dplls(void)
258 u32 sys_clk_khz, abe_ref_clk;
259 u32 sysclk_ind, sd_div, num, den;
260 const struct dpll_params *params;
262 sysclk_ind = get_sys_clk_index();
263 sys_clk_khz = get_sys_clk_freq() / 1000;
266 clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
267 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
269 params = get_iva_dpll_params();
270 do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK);
274 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
275 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
276 * - where CLKINP is sys_clk in MHz
277 * Use CLKINP in KHz and adjust the denominator accordingly so
278 * that we have enough accuracy and at the same time no overflow
280 params = get_usb_dpll_params();
281 num = params->m * sys_clk_khz;
282 den = (params->n + 1) * 250 * 1000;
285 clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
286 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
287 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
289 /* Now setup the dpll with the regular function */
290 do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK);
292 /* Configure ABE dpll */
293 params = get_abe_dpll_params();
294 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
295 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
297 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
299 * We need to enable some additional options to achieve
300 * 196.608MHz from 32768 Hz
302 setbits_le32(&prcm->cm_clkmode_dpll_abe,
303 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
304 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
305 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
306 CM_CLKMODE_DPLL_REGM4XEN_MASK);
307 /* Spend 4 REFCLK cycles at each stage */
308 clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
309 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
310 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
313 /* Select the right reference clk */
314 clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
315 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
316 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
318 do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
321 void do_scale_tps62361(u32 reg, u32 volt_mv)
325 step = volt_mv - TPS62361_BASE_VOLT_MV;
329 * Select SET1 in TPS62361:
330 * VSEL1 is grounded on board. So the following selects
331 * VSEL1 = 0 and VSEL0 = 1
333 gpio_direction_output(TPS62361_VSEL0_GPIO, 0);
334 gpio_set_value(TPS62361_VSEL0_GPIO, 1);
336 temp = TPS62361_I2C_SLAVE_ADDR |
337 (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
338 (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
339 PRM_VC_VAL_BYPASS_VALID_BIT;
340 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
342 writel(temp, &prcm->prm_vc_val_bypass);
343 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
344 &prcm->prm_vc_val_bypass, LDELAY)) {
345 puts("Scaling voltage failed for vdd_mpu from TPS\n");
349 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
351 u32 temp, offset_code;
352 u32 step = 12660; /* 12.66 mV represented in uV */
353 u32 offset = volt_mv;
355 /* convert to uV for better accuracy in the calculations */
358 if (omap_revision() == OMAP4430_ES1_0)
359 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
361 offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
363 offset_code = (offset + step - 1) / step;
364 /* The code starts at 1 not 0 */
367 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
370 temp = SMPS_I2C_SLAVE_ADDR |
371 (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
372 (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
373 PRM_VC_VAL_BYPASS_VALID_BIT;
374 writel(temp, &prcm->prm_vc_val_bypass);
375 if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
376 &prcm->prm_vc_val_bypass, LDELAY)) {
377 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
381 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
383 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
384 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
385 debug("Enable clock domain - %p\n", clkctrl_reg);
388 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
390 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
393 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
394 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
396 clkctrl = readl(clkctrl_addr);
397 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
398 MODULE_CLKCTRL_IDLEST_SHIFT;
400 printf("Clock enable failed for 0x%p idlest 0x%x\n",
401 clkctrl_addr, clkctrl);
407 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
410 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
411 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
412 debug("Enable clock module - %p\n", clkctrl_addr);
414 wait_for_clk_enable(clkctrl_addr);
417 void freq_update_core(void)
419 u32 freq_config1 = 0;
420 const struct dpll_params *core_dpll_params;
422 core_dpll_params = get_core_dpll_params();
423 /* Put EMIF clock domain in sw wakeup mode */
424 enable_clock_domain(&prcm->cm_memif_clkstctrl,
425 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
426 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
427 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
429 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
430 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
432 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
433 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
435 freq_config1 |= (core_dpll_params->m2 <<
436 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
437 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
439 writel(freq_config1, &prcm->cm_shadow_freq_config1);
440 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
441 &prcm->cm_shadow_freq_config1, LDELAY)) {
442 puts("FREQ UPDATE procedure failed!!");
446 /* Put EMIF clock domain back in hw auto mode */
447 enable_clock_domain(&prcm->cm_memif_clkstctrl,
448 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
449 wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
450 wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
453 void bypass_dpll(u32 *const base)
455 do_bypass_dpll(base);
456 wait_for_bypass(base);
459 void lock_dpll(u32 *const base)
465 void setup_clocks_for_console(void)
467 /* Do not add any spl_debug prints in this function */
468 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
469 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
470 CD_CLKCTRL_CLKTRCTRL_SHIFT);
472 /* Enable all UARTs - console will be on one of them */
473 clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
474 MODULE_CLKCTRL_MODULEMODE_MASK,
475 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
476 MODULE_CLKCTRL_MODULEMODE_SHIFT);
478 clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
479 MODULE_CLKCTRL_MODULEMODE_MASK,
480 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
481 MODULE_CLKCTRL_MODULEMODE_SHIFT);
483 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
484 MODULE_CLKCTRL_MODULEMODE_MASK,
485 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
486 MODULE_CLKCTRL_MODULEMODE_SHIFT);
488 clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
489 MODULE_CLKCTRL_MODULEMODE_MASK,
490 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
491 MODULE_CLKCTRL_MODULEMODE_SHIFT);
493 clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
494 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
495 CD_CLKCTRL_CLKTRCTRL_SHIFT);
498 void setup_sri2c(void)
500 u32 sys_clk_khz, cycles_hi, cycles_low, temp;
502 sys_clk_khz = get_sys_clk_freq() / 1000;
505 * Setup the dedicated I2C controller for Voltage Control
506 * I2C clk - high period 40% low period 60%
508 cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
509 cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
510 /* values to be set in register - less by 5 & 7 respectively */
513 temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
514 (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
515 writel(temp, &prcm->prm_vc_cfg_i2c_clk);
517 /* Disable high speed mode and all advanced features */
518 writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
521 void do_enable_clocks(u32 *const *clk_domains,
522 u32 *const *clk_modules_hw_auto,
523 u32 *const *clk_modules_explicit_en,
528 /* Put the clock domains in SW_WKUP mode */
529 for (i = 0; (i < max) && clk_domains[i]; i++) {
530 enable_clock_domain(clk_domains[i],
531 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
534 /* Clock modules that need to be put in HW_AUTO */
535 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
536 enable_clock_module(clk_modules_hw_auto[i],
537 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
541 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
542 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
543 enable_clock_module(clk_modules_explicit_en[i],
544 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
548 /* Put the clock domains in HW_AUTO mode now */
549 for (i = 0; (i < max) && clk_domains[i]; i++) {
550 enable_clock_domain(clk_domains[i],
551 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
557 switch (omap_hw_init_context()) {
558 case OMAP_INIT_CONTEXT_SPL:
559 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
560 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
561 enable_basic_clocks();
564 setup_non_essential_dplls();
565 enable_non_essential_clocks();