2 * code for switching cores into non-secure state and into HYP mode
4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <linux/linkage.h>
28 #include <asm/armv7.h>
33 /* the vector table for secure state and HYP mode */
37 adr pc, _secure_monitor
45 * secure monitor handler
46 * U-boot calls this "software interrupt" in start.S
47 * This is executed on a "smc" instruction, we use a "smc #0" to switch
48 * to non-secure state.
49 * We use only r0 and r1 here, due to constraints in the caller.
53 mrc p15, 0, r1, c1, c1, 0 @ read SCR
54 bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
55 orr r1, r1, #0x31 @ enable NS, AW, FW bits
57 #ifdef CONFIG_ARMV7_VIRT
58 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
59 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
60 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
61 orreq r1, r1, #0x100 @ allow HVC instruction
64 mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
66 #ifdef CONFIG_ARMV7_VIRT
67 mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
68 mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
71 movs pc, lr @ return to non-secure SVC
74 mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
75 mov pc, lr @ do no switch modes, but
79 * Secondary CPUs start here and call the code for the core specific parts
80 * of the non-secure and HYP mode transition. The GIC distributor specific
81 * code has already been executed by a C function before.
82 * Then they go back to wfi and wait to be woken up by the kernel again.
87 msr cpsr, r0 @ disable interrupts
89 mcr p15, 0, r1, c12, c0, 0 @ set VBAR
92 mov r12, r0 @ save GICC address
93 #ifdef CONFIG_ARMV7_VIRT
97 ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
98 str r1, [r12, #GICC_EOIR] @ signal end of interrupt
100 adr r0, _smp_pen @ do not use this address again
101 b smp_waitloop @ wait for IPIs, board specific
105 * Switch a core to non-secure state.
107 * 1. initialize the GIC per-core interface
108 * 2. allow coprocessor access in non-secure modes
109 * 3. switch the cpu mode (by calling "smc #0")
111 * Called from smp_pen by secondary cores and directly by the BSP.
112 * Do not assume that the stack is available and only use registers
115 * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
116 * though, but we check this in C before calling this function.
119 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
120 ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
122 mrc p15, 4, r2, c15, c0, 0 @ read CBAR
123 bfc r2, #0, #15 @ clear reserved bits
125 add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
126 mvn r1, #0 @ all bits to 1
127 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
129 mrc p15, 0, r0, c0, c0, 0 @ read MIDR
130 ldr r1, =MIDR_PRIMARY_PART_MASK
131 and r0, r0, r1 @ mask out variant and revision
133 ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
134 cmp r0, r1 @ check for Cortex-A7
136 ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
137 cmpne r0, r1 @ check for Cortex-A15
139 movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
140 moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
141 add r3, r2, r1 @ r3 = GIC CPU i/f addr
143 mov r1, #1 @ set GICC_CTLR[enable]
144 str r1, [r3, #GICC_CTLR] @ and clear all other bits
146 str r1, [r3, #GICC_PMR] @ set priority mask register
150 mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
152 /* The CNTFRQ register of the generic timer needs to be
153 * programmed in secure state. Some primary bootloaders / firmware
154 * omit this, so if the frequency is provided in the configuration,
155 * we do this here instead.
156 * But first check if we have the generic timer.
158 #ifdef CONFIG_SYS_CLK_FREQ
159 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
160 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
161 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
162 ldreq r1, =CONFIG_SYS_CLK_FREQ
163 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
166 adr r1, _monitor_vectors
167 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
169 mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
172 smc #0 @ call into MONITOR mode
174 mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
177 str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
178 add r2, r2, #GIC_DIST_OFFSET
179 str r1, [r2, #GICD_CTLR] @ allow private interrupts
181 mov r0, r3 @ return GICC address
184 ENDPROC(_nonsec_init)
186 #ifdef CONFIG_SMP_PEN_ADDR
187 /* void __weak smp_waitloop(unsigned previous_address); */
190 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
192 cmp r0, r1 @ make sure we dont execute this code
193 beq smp_waitloop @ again (due to a spurious wakeup)
195 ENDPROC(smp_waitloop)
199 ENTRY(_switch_to_hyp)
201 mov r1, sp @ save SVC copy of LR and SP
203 hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
205 mov lr, r0 @ restore SVC copy of LR and SP
208 ENDPROC(_switch_to_hyp)