2 * code for switching cores into non-secure state and into HYP mode
4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/linkage.h>
12 #include <asm/armv7.h>
18 /* the vector table for secure state and HYP mode */
22 adr pc, _secure_monitor
30 * secure monitor handler
31 * U-boot calls this "software interrupt" in start.S
32 * This is executed on a "smc" instruction, we use a "smc #0" to switch
33 * to non-secure state.
34 * We use only r0 and r1 here, due to constraints in the caller.
37 mrc p15, 0, r1, c1, c1, 0 @ read SCR
38 bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
39 orr r1, r1, #0x31 @ enable NS, AW, FW bits
41 #ifdef CONFIG_ARMV7_VIRT
42 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
43 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
44 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
45 orreq r1, r1, #0x100 @ allow HVC instruction
48 mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
51 #ifdef CONFIG_ARMV7_VIRT
52 mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value
53 mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR
56 movs pc, lr @ return to non-secure SVC
59 mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
60 mov pc, lr @ do no switch modes, but
64 * Secondary CPUs start here and call the code for the core specific parts
65 * of the non-secure and HYP mode transition. The GIC distributor specific
66 * code has already been executed by a C function before.
67 * Then they go back to wfi and wait to be woken up by the kernel again.
72 msr cpsr, r0 @ disable interrupts
74 mcr p15, 0, r1, c12, c0, 0 @ set VBAR
77 mov r12, r0 @ save GICC address
78 #ifdef CONFIG_ARMV7_VIRT
82 ldr r1, [r12, #GICC_IAR] @ acknowledge IPI
83 str r1, [r12, #GICC_EOIR] @ signal end of interrupt
85 adr r0, _smp_pen @ do not use this address again
86 b smp_waitloop @ wait for IPIs, board specific
90 * Switch a core to non-secure state.
92 * 1. initialize the GIC per-core interface
93 * 2. allow coprocessor access in non-secure modes
94 * 3. switch the cpu mode (by calling "smc #0")
96 * Called from smp_pen by secondary cores and directly by the BSP.
97 * Do not assume that the stack is available and only use registers
100 * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
101 * though, but we check this in C before calling this function.
104 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
105 ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
107 mrc p15, 4, r2, c15, c0, 0 @ read CBAR
108 bfc r2, #0, #15 @ clear reserved bits
110 add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
111 mvn r1, #0 @ all bits to 1
112 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
114 mrc p15, 0, r0, c0, c0, 0 @ read MIDR
115 ldr r1, =MIDR_PRIMARY_PART_MASK
116 and r0, r0, r1 @ mask out variant and revision
118 ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
119 cmp r0, r1 @ check for Cortex-A7
121 ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
122 cmpne r0, r1 @ check for Cortex-A15
124 movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
125 moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
126 add r3, r2, r1 @ r3 = GIC CPU i/f addr
128 mov r1, #1 @ set GICC_CTLR[enable]
129 str r1, [r3, #GICC_CTLR] @ and clear all other bits
131 str r1, [r3, #GICC_PMR] @ set priority mask register
135 mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
137 /* The CNTFRQ register of the generic timer needs to be
138 * programmed in secure state. Some primary bootloaders / firmware
139 * omit this, so if the frequency is provided in the configuration,
140 * we do this here instead.
141 * But first check if we have the generic timer.
143 #ifdef CONFIG_SYS_CLK_FREQ
144 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
145 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
146 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
147 ldreq r1, =CONFIG_SYS_CLK_FREQ
148 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
151 adr r1, _monitor_vectors
152 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
154 mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
157 smc #0 @ call into MONITOR mode
159 mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
162 str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
163 add r2, r2, #GIC_DIST_OFFSET
164 str r1, [r2, #GICD_CTLR] @ allow private interrupts
166 mov r0, r3 @ return GICC address
169 ENDPROC(_nonsec_init)
171 #ifdef CONFIG_SMP_PEN_ADDR
172 /* void __weak smp_waitloop(unsigned previous_address); */
175 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
177 cmp r0, r1 @ make sure we dont execute this code
178 beq smp_waitloop @ again (due to a spurious wakeup)
180 ENDPROC(smp_waitloop)
184 ENTRY(_switch_to_hyp)
186 mov r1, sp @ save SVC copy of LR and SP
188 hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
190 mov lr, r0 @ restore SVC copy of LR and SP
193 ENDPROC(_switch_to_hyp)