2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/imx-common/boot_mode.h>
13 #include <asm/imx-common/dma.h>
14 #include <asm/arch/crm_regs.h>
16 #include <imx_thermal.h>
18 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
20 #if defined(CONFIG_IMX_THERMAL)
21 static const struct imx_thermal_plat imx7_thermal_plat = {
22 .regs = (void *)ANATOP_BASE_ADDR,
27 U_BOOT_DEVICE(imx7_thermal) = {
28 .name = "imx_thermal",
29 .platdata = &imx7_thermal_plat,
34 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
35 * defines a 2-bit SPEED_GRADING
37 #define OCOTP_TESTER3_SPEED_SHIFT 8
38 #define OCOTP_TESTER3_SPEED_800MHZ 0
39 #define OCOTP_TESTER3_SPEED_850MHZ 1
40 #define OCOTP_TESTER3_SPEED_1GHZ 2
42 u32 get_cpu_speed_grade_hz(void)
44 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
45 struct fuse_bank *bank = &ocotp->bank[1];
46 struct fuse_bank1_regs *fuse =
47 (struct fuse_bank1_regs *)bank->fuse_regs;
50 val = readl(&fuse->tester3);
51 val >>= OCOTP_TESTER3_SPEED_SHIFT;
55 case OCOTP_TESTER3_SPEED_800MHZ:
57 case OCOTP_TESTER3_SPEED_850MHZ:
59 case OCOTP_TESTER3_SPEED_1GHZ:
66 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
67 * defines a 2-bit SPEED_GRADING
69 #define OCOTP_TESTER3_TEMP_SHIFT 6
71 u32 get_cpu_temp_grade(int *minc, int *maxc)
73 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
74 struct fuse_bank *bank = &ocotp->bank[1];
75 struct fuse_bank1_regs *fuse =
76 (struct fuse_bank1_regs *)bank->fuse_regs;
79 val = readl(&fuse->tester3);
80 val >>= OCOTP_TESTER3_TEMP_SHIFT;
84 if ( val == TEMP_AUTOMOTIVE) {
87 } else if (val == TEMP_INDUSTRIAL) {
90 } else if (val == TEMP_EXTCOMMERCIAL) {
101 u32 get_cpu_rev(void)
103 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
105 u32 reg = readl(&ccm_anatop->digprog);
106 u32 type = (reg >> 16) & 0xff;
109 return (type << 12) | reg;
112 #ifdef CONFIG_REVISION_TAG
113 u32 __weak get_board_rev(void)
115 return get_cpu_rev();
119 int arch_cpu_init(void)
123 /* Disable PDE bit of WMCR register */
124 imx_set_wdog_powerdown(false);
126 #ifdef CONFIG_APBH_DMA
134 #ifdef CONFIG_SERIAL_TAG
135 void get_board_serial(struct tag_serialnr *serialnr)
137 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
138 struct fuse_bank *bank = &ocotp->bank[0];
139 struct fuse_bank0_regs *fuse =
140 (struct fuse_bank0_regs *)bank->fuse_regs;
142 serialnr->low = fuse->tester0;
143 serialnr->high = fuse->tester1;
147 #if defined(CONFIG_FEC_MXC)
148 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
150 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
151 struct fuse_bank *bank = &ocotp->bank[9];
152 struct fuse_bank9_regs *fuse =
153 (struct fuse_bank9_regs *)bank->fuse_regs;
156 u32 value = readl(&fuse->mac_addr1);
157 mac[0] = (value >> 8);
160 value = readl(&fuse->mac_addr0);
161 mac[2] = value >> 24;
162 mac[3] = value >> 16;
166 u32 value = readl(&fuse->mac_addr2);
167 mac[0] = value >> 24;
168 mac[1] = value >> 16;
172 value = readl(&fuse->mac_addr1);
173 mac[4] = value >> 24;
174 mac[5] = value >> 16;
179 void set_wdog_reset(struct wdog_regs *wdog)
181 u32 reg = readw(&wdog->wcr);
183 * Output WDOG_B signal to reset external pmic or POR_B decided by
184 * the board desgin. Without external reset, the peripherals/DDR/
185 * PMIC are not reset, that may cause system working abnormal.
187 reg = readw(&wdog->wcr);
190 * WDZST bit is write-once only bit. Align this bit in kernel,
191 * otherwise kernel code will have no chance to set this bit.
194 writew(reg, &wdog->wcr);
198 * cfg_val will be used for
199 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
200 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
201 * to SBMR1, which will determine the boot device.
203 const struct boot_mode soc_boot_modes[] = {
204 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
205 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
206 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
207 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
209 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
210 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
211 /* 4 bit bus width */
212 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
213 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
214 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
215 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
216 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
217 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
221 enum boot_device get_boot_device(void)
223 struct bootrom_sw_info **p =
224 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
226 enum boot_device boot_dev = SD1_BOOT;
227 u8 boot_type = (*p)->boot_dev_type;
228 u8 boot_instance = (*p)->boot_dev_instance;
232 boot_dev = boot_instance + SD1_BOOT;
235 boot_dev = boot_instance + MMC1_BOOT;
238 boot_dev = NAND_BOOT;
241 boot_dev = QSPI_BOOT;
244 boot_dev = WEIM_NOR_BOOT;
246 case BOOT_TYPE_SPINOR:
247 boot_dev = SPI_NOR_BOOT;
258 #if !defined CONFIG_SPL_BUILD
259 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
261 "mrc p15, 0, r0, c1, c0, 1\n"
262 "orr r0, r0, #1 << 6\n"
263 "mcr p15, 0, r0, c1, c0, 1\n");
265 /* clock configuration. */