3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/dma.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/bootm.h>
26 #include <imx_thermal.h>
42 #if defined(CONFIG_IMX6_THERMAL)
43 static const struct imx_thermal_plat imx6_thermal_plat = {
44 .regs = (void *)ANATOP_BASE_ADDR,
49 U_BOOT_DEVICE(imx6_thermal) = {
50 .name = "imx_thermal",
51 .platdata = &imx6_thermal_plat,
57 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
58 return readl(&scu->config) & 3;
63 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
64 u32 reg = readl(&anatop->digprog_sololite);
65 u32 type = ((reg >> 16) & 0xff);
67 if (type != MXC_CPU_MX6SL) {
68 reg = readl(&anatop->digprog);
69 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
70 u32 cfg = readl(&scu->config) & 3;
71 type = ((reg >> 16) & 0xff);
72 if (type == MXC_CPU_MX6DL) {
74 type = MXC_CPU_MX6SOLO;
77 if (type == MXC_CPU_MX6Q) {
83 reg &= 0xff; /* mx6 silicon revision */
84 return (type << 12) | (reg + 0x10);
87 #ifdef CONFIG_REVISION_TAG
88 u32 __weak get_board_rev(void)
90 u32 cpurev = get_cpu_rev();
91 u32 type = ((cpurev >> 12) & 0xff);
92 if (type == MXC_CPU_MX6SOLO)
93 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
95 if (type == MXC_CPU_MX6D)
96 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
104 struct aipstz_regs *aips1, *aips2;
106 struct aipstz_regs *aips3;
109 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
110 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
112 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
116 * Set all MPROTx to be non-bufferable, trusted for R/W,
117 * not forced to user-mode.
119 writel(0x77777777, &aips1->mprot0);
120 writel(0x77777777, &aips1->mprot1);
121 writel(0x77777777, &aips2->mprot0);
122 writel(0x77777777, &aips2->mprot1);
125 * Set all OPACRx to be non-bufferable, not require
126 * supervisor privilege level for access,allow for
127 * write access and untrusted master access.
129 writel(0x00000000, &aips1->opacr0);
130 writel(0x00000000, &aips1->opacr1);
131 writel(0x00000000, &aips1->opacr2);
132 writel(0x00000000, &aips1->opacr3);
133 writel(0x00000000, &aips1->opacr4);
134 writel(0x00000000, &aips2->opacr0);
135 writel(0x00000000, &aips2->opacr1);
136 writel(0x00000000, &aips2->opacr2);
137 writel(0x00000000, &aips2->opacr3);
138 writel(0x00000000, &aips2->opacr4);
142 * Set all MPROTx to be non-bufferable, trusted for R/W,
143 * not forced to user-mode.
145 writel(0x77777777, &aips3->mprot0);
146 writel(0x77777777, &aips3->mprot1);
149 * Set all OPACRx to be non-bufferable, not require
150 * supervisor privilege level for access,allow for
151 * write access and untrusted master access.
153 writel(0x00000000, &aips3->opacr0);
154 writel(0x00000000, &aips3->opacr1);
155 writel(0x00000000, &aips3->opacr2);
156 writel(0x00000000, &aips3->opacr3);
157 writel(0x00000000, &aips3->opacr4);
161 static void clear_ldo_ramp(void)
163 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
166 /* ROM may modify LDO ramp up time according to fuse setting, so in
167 * order to be in the safe side we neeed to reset these settings to
168 * match the reset value: 0'b00
170 reg = readl(&anatop->ana_misc2);
171 reg &= ~(0x3f << 24);
172 writel(reg, &anatop->ana_misc2);
176 * Set the PMU_REG_CORE register
178 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
179 * Possible values are from 0.725V to 1.450V in steps of
182 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
184 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
185 u32 val, step, old, reg = readl(&anatop->reg_core);
189 val = 0x00; /* Power gated off */
191 val = 0x1F; /* Power FET switched full on. No regulation */
193 val = (mv - 700) / 25;
211 old = (reg & (0x1F << shift)) >> shift;
212 step = abs(val - old);
216 reg = (reg & ~(0x1F << shift)) | (val << shift);
217 writel(reg, &anatop->reg_core);
220 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
228 static void imx_set_wdog_powerdown(bool enable)
230 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
231 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
233 /* Write to the PDE (Power Down Enable) bit */
234 writew(enable, &wdog1->wmcr);
235 writew(enable, &wdog2->wmcr);
238 static void set_ahb_rate(u32 val)
240 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
243 div = get_periph_clk() / val - 1;
244 reg = readl(&mxc_ccm->cbcdr);
246 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
247 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
250 static void clear_mmdc_ch_mask(void)
252 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
254 /* Clear MMDC channel mask */
255 writel(0, &mxc_ccm->ccdr);
259 static void set_preclk_from_osc(void)
261 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
264 reg = readl(&mxc_ccm->cscmr1);
265 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
266 writel(reg, &mxc_ccm->cscmr1);
270 int arch_cpu_init(void)
274 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
275 clear_mmdc_ch_mask();
278 * When low freq boot is enabled, ROM will not set AHB
279 * freq, so we need to ensure AHB freq is 132MHz in such
282 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
283 set_ahb_rate(132000000);
285 /* Set perclk to source from OSC 24MHz */
286 #if defined(CONFIG_MX6SL)
287 set_preclk_from_osc();
290 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
292 #ifdef CONFIG_APBH_DMA
300 int board_postclk_init(void)
302 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
307 #ifndef CONFIG_SYS_DCACHE_OFF
308 void enable_caches(void)
310 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
311 enum dcache_option option = DCACHE_WRITETHROUGH;
313 enum dcache_option option = DCACHE_WRITEBACK;
316 /* Avoid random hang when download by usb */
317 invalidate_dcache_all();
319 /* Enable D-cache. I-cache is already enabled in start.S */
322 /* Enable caching on OCRAM and ROM */
323 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
326 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
332 #if defined(CONFIG_FEC_MXC)
333 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
335 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
336 struct fuse_bank *bank = &ocotp->bank[4];
337 struct fuse_bank4_regs *fuse =
338 (struct fuse_bank4_regs *)bank->fuse_regs;
340 u32 value = readl(&fuse->mac_addr_high);
341 mac[0] = (value >> 8);
344 value = readl(&fuse->mac_addr_low);
345 mac[2] = value >> 24 ;
346 mac[3] = value >> 16 ;
347 mac[4] = value >> 8 ;
353 void boot_mode_apply(unsigned cfg_val)
356 struct src *psrc = (struct src *)SRC_BASE_ADDR;
357 writel(cfg_val, &psrc->gpr9);
358 reg = readl(&psrc->gpr10);
363 writel(reg, &psrc->gpr10);
366 * cfg_val will be used for
367 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
368 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
369 * instead of SBMR1 to determine the boot device.
371 const struct boot_mode soc_boot_modes[] = {
372 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
373 /* reserved value should start rom usb */
374 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
375 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
376 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
377 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
378 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
379 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
380 /* 4 bit bus width */
381 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
382 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
383 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
384 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
390 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
391 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
394 u32 reg, periph1, periph2;
396 if (is_cpu_type(MXC_CPU_MX6SX))
399 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
400 * to make sure PFD is working right, otherwise, PFDs may
401 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
402 * workaround in ROM code, as bus clock need it
405 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
406 ANATOP_PFD_CLKGATE_MASK(1) |
407 ANATOP_PFD_CLKGATE_MASK(2) |
408 ANATOP_PFD_CLKGATE_MASK(3);
409 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
410 ANATOP_PFD_CLKGATE_MASK(3);
412 reg = readl(&ccm->cbcmr);
413 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
414 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
415 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
416 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
418 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
419 if ((periph2 != 0x2) && (periph1 != 0x2))
420 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
422 if ((periph2 != 0x1) && (periph1 != 0x1) &&
423 (periph2 != 0x3) && (periph1 != 0x3))
424 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
426 writel(mask480, &anatop->pfd_480_set);
427 writel(mask528, &anatop->pfd_528_set);
428 writel(mask480, &anatop->pfd_480_clr);
429 writel(mask528, &anatop->pfd_528_clr);
432 #ifdef CONFIG_IMX_HDMI
433 void imx_enable_hdmi_phy(void)
435 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
437 reg = readb(&hdmi->phy_conf0);
438 reg |= HDMI_PHY_CONF0_PDZ_MASK;
439 writeb(reg, &hdmi->phy_conf0);
441 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
442 writeb(reg, &hdmi->phy_conf0);
444 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
445 writeb(reg, &hdmi->phy_conf0);
446 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
449 void imx_setup_hdmi(void)
451 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
452 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
455 /* Turn on HDMI PHY clock */
456 reg = readl(&mxc_ccm->CCGR2);
457 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
458 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
459 writel(reg, &mxc_ccm->CCGR2);
460 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
461 reg = readl(&mxc_ccm->chsccdr);
462 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
463 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
464 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
465 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
466 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
467 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
468 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
469 writel(reg, &mxc_ccm->chsccdr);
473 #ifndef CONFIG_SYS_L2CACHE_OFF
474 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
475 void v7_outer_cache_enable(void)
477 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
480 #if defined CONFIG_MX6SL
481 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
482 val = readl(&iomux->gpr[11]);
483 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
484 /* L2 cache configured as OCRAM, reset it */
485 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
486 writel(val, &iomux->gpr[11]);
490 /* Must disable the L2 before changing the latency parameters */
491 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
493 writel(0x132, &pl310->pl310_tag_latency_ctrl);
494 writel(0x132, &pl310->pl310_data_latency_ctrl);
496 val = readl(&pl310->pl310_prefetch_ctrl);
498 /* Turn on the L2 I/D prefetch */
502 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
503 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
504 * But according to ARM PL310 errata: 752271
505 * ID: 752271: Double linefill feature can cause data corruption
506 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
507 * Workaround: The only workaround to this erratum is to disable the
508 * double linefill feature. This is the default behavior.
514 writel(val, &pl310->pl310_prefetch_ctrl);
516 val = readl(&pl310->pl310_power_ctrl);
517 val |= L2X0_DYNAMIC_CLK_GATING_EN;
518 val |= L2X0_STNDBY_MODE_EN;
519 writel(val, &pl310->pl310_power_ctrl);
521 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
524 void v7_outer_cache_disable(void)
526 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
528 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
530 #endif /* !CONFIG_SYS_L2CACHE_OFF */