3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
32 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
33 u32 reg = readl(&anatop->digprog_sololite);
34 u32 type = ((reg >> 16) & 0xff);
36 if (type != MXC_CPU_MX6SL) {
37 reg = readl(&anatop->digprog);
38 type = ((reg >> 16) & 0xff);
39 if (type == MXC_CPU_MX6DL) {
40 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
41 u32 cfg = readl(&scu->config) & 3;
44 type = MXC_CPU_MX6SOLO;
47 reg &= 0xff; /* mx6 silicon revision */
48 return (type << 12) | (reg + 0x10);
51 #ifdef CONFIG_REVISION_TAG
52 u32 __weak get_board_rev(void)
54 u32 cpurev = get_cpu_rev();
55 u32 type = ((cpurev >> 12) & 0xff);
56 if (type == MXC_CPU_MX6SOLO)
57 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
65 struct aipstz_regs *aips1, *aips2;
67 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
68 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
71 * Set all MPROTx to be non-bufferable, trusted for R/W,
72 * not forced to user-mode.
74 writel(0x77777777, &aips1->mprot0);
75 writel(0x77777777, &aips1->mprot1);
76 writel(0x77777777, &aips2->mprot0);
77 writel(0x77777777, &aips2->mprot1);
80 * Set all OPACRx to be non-bufferable, not require
81 * supervisor privilege level for access,allow for
82 * write access and untrusted master access.
84 writel(0x00000000, &aips1->opacr0);
85 writel(0x00000000, &aips1->opacr1);
86 writel(0x00000000, &aips1->opacr2);
87 writel(0x00000000, &aips1->opacr3);
88 writel(0x00000000, &aips1->opacr4);
89 writel(0x00000000, &aips2->opacr0);
90 writel(0x00000000, &aips2->opacr1);
91 writel(0x00000000, &aips2->opacr2);
92 writel(0x00000000, &aips2->opacr3);
93 writel(0x00000000, &aips2->opacr4);
99 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
100 * them to the specified millivolt level.
101 * Possible values are from 0.725V to 1.450V in steps of
104 static void set_vddsoc(u32 mv)
106 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
107 u32 val, reg = readl(&anatop->reg_core);
110 val = 0x00; /* Power gated off */
112 val = 0x1F; /* Power FET switched full on. No regulation */
114 val = (mv - 700) / 25;
117 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
118 * and set them to the calculated value (0.7V + val * 0.25V)
120 reg = (reg & ~(0x1F << 18)) | (val << 18);
121 writel(reg, &anatop->reg_core);
124 static void imx_set_wdog_powerdown(bool enable)
126 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
127 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
129 /* Write to the PDE (Power Down Enable) bit */
130 writew(enable, &wdog1->wmcr);
131 writew(enable, &wdog2->wmcr);
134 int arch_cpu_init(void)
138 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
140 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
142 #ifdef CONFIG_APBH_DMA
150 #ifndef CONFIG_SYS_DCACHE_OFF
151 void enable_caches(void)
153 /* Avoid random hang when download by usb */
154 invalidate_dcache_all();
155 /* Enable D-cache. I-cache is already enabled in start.S */
160 #if defined(CONFIG_FEC_MXC)
161 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
163 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
164 struct fuse_bank *bank = &ocotp->bank[4];
165 struct fuse_bank4_regs *fuse =
166 (struct fuse_bank4_regs *)bank->fuse_regs;
168 u32 value = readl(&fuse->mac_addr_high);
169 mac[0] = (value >> 8);
172 value = readl(&fuse->mac_addr_low);
173 mac[2] = value >> 24 ;
174 mac[3] = value >> 16 ;
175 mac[4] = value >> 8 ;
181 void boot_mode_apply(unsigned cfg_val)
184 struct src *psrc = (struct src *)SRC_BASE_ADDR;
185 writel(cfg_val, &psrc->gpr9);
186 reg = readl(&psrc->gpr10);
191 writel(reg, &psrc->gpr10);
194 * cfg_val will be used for
195 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
196 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
197 * to SBMR1, which will determine the boot device.
199 const struct boot_mode soc_boot_modes[] = {
200 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
201 /* reserved value should start rom usb */
202 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
203 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
204 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
205 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
206 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
207 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
208 /* 4 bit bus width */
209 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
210 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
211 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
212 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
218 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
219 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
223 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
224 * to make sure PFD is working right, otherwise, PFDs may
225 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
226 * workaround in ROM code, as bus clock need it
229 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
230 ANATOP_PFD_CLKGATE_MASK(1) |
231 ANATOP_PFD_CLKGATE_MASK(2) |
232 ANATOP_PFD_CLKGATE_MASK(3);
233 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
234 ANATOP_PFD_CLKGATE_MASK(1) |
235 ANATOP_PFD_CLKGATE_MASK(3);
238 * Don't reset PFD2 on DL/S
241 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
242 writel(mask480, &anatop->pfd_480_set);
243 writel(mask528, &anatop->pfd_528_set);
244 writel(mask480, &anatop->pfd_480_clr);
245 writel(mask528, &anatop->pfd_528_clr);
248 #ifdef CONFIG_IMX_HDMI
249 void imx_enable_hdmi_phy(void)
251 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
253 reg = readb(&hdmi->phy_conf0);
254 reg |= HDMI_PHY_CONF0_PDZ_MASK;
255 writeb(reg, &hdmi->phy_conf0);
257 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
258 writeb(reg, &hdmi->phy_conf0);
260 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
261 writeb(reg, &hdmi->phy_conf0);
262 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
265 void imx_setup_hdmi(void)
267 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
268 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
271 /* Turn on HDMI PHY clock */
272 reg = readl(&mxc_ccm->CCGR2);
273 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
274 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
275 writel(reg, &mxc_ccm->CCGR2);
276 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
277 reg = readl(&mxc_ccm->chsccdr);
278 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
279 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
280 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
281 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
282 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
283 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
284 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
285 writel(reg, &mxc_ccm->chsccdr);