3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/pl310.h>
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/imx-common/dma.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
40 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
41 u32 reg = readl(&anatop->digprog_sololite);
42 u32 type = ((reg >> 16) & 0xff);
44 if (type != MXC_CPU_MX6SL) {
45 reg = readl(&anatop->digprog);
46 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
47 u32 cfg = readl(&scu->config) & 3;
48 type = ((reg >> 16) & 0xff);
49 if (type == MXC_CPU_MX6DL) {
51 type = MXC_CPU_MX6SOLO;
54 if (type == MXC_CPU_MX6Q) {
60 reg &= 0xff; /* mx6 silicon revision */
61 return (type << 12) | (reg + 0x10);
64 #ifdef CONFIG_REVISION_TAG
65 u32 __weak get_board_rev(void)
67 u32 cpurev = get_cpu_rev();
68 u32 type = ((cpurev >> 12) & 0xff);
69 if (type == MXC_CPU_MX6SOLO)
70 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
72 if (type == MXC_CPU_MX6D)
73 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
81 struct aipstz_regs *aips1, *aips2;
83 struct aipstz_regs *aips3;
86 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
87 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
89 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
93 * Set all MPROTx to be non-bufferable, trusted for R/W,
94 * not forced to user-mode.
96 writel(0x77777777, &aips1->mprot0);
97 writel(0x77777777, &aips1->mprot1);
98 writel(0x77777777, &aips2->mprot0);
99 writel(0x77777777, &aips2->mprot1);
102 * Set all OPACRx to be non-bufferable, not require
103 * supervisor privilege level for access,allow for
104 * write access and untrusted master access.
106 writel(0x00000000, &aips1->opacr0);
107 writel(0x00000000, &aips1->opacr1);
108 writel(0x00000000, &aips1->opacr2);
109 writel(0x00000000, &aips1->opacr3);
110 writel(0x00000000, &aips1->opacr4);
111 writel(0x00000000, &aips2->opacr0);
112 writel(0x00000000, &aips2->opacr1);
113 writel(0x00000000, &aips2->opacr2);
114 writel(0x00000000, &aips2->opacr3);
115 writel(0x00000000, &aips2->opacr4);
119 * Set all MPROTx to be non-bufferable, trusted for R/W,
120 * not forced to user-mode.
122 writel(0x77777777, &aips3->mprot0);
123 writel(0x77777777, &aips3->mprot1);
126 * Set all OPACRx to be non-bufferable, not require
127 * supervisor privilege level for access,allow for
128 * write access and untrusted master access.
130 writel(0x00000000, &aips3->opacr0);
131 writel(0x00000000, &aips3->opacr1);
132 writel(0x00000000, &aips3->opacr2);
133 writel(0x00000000, &aips3->opacr3);
134 writel(0x00000000, &aips3->opacr4);
138 static void clear_ldo_ramp(void)
140 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
143 /* ROM may modify LDO ramp up time according to fuse setting, so in
144 * order to be in the safe side we neeed to reset these settings to
145 * match the reset value: 0'b00
147 reg = readl(&anatop->ana_misc2);
148 reg &= ~(0x3f << 24);
149 writel(reg, &anatop->ana_misc2);
153 * Set the PMU_REG_CORE register
155 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
156 * Possible values are from 0.725V to 1.450V in steps of
159 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
161 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
162 u32 val, step, old, reg = readl(&anatop->reg_core);
166 val = 0x00; /* Power gated off */
168 val = 0x1F; /* Power FET switched full on. No regulation */
170 val = (mv - 700) / 25;
188 old = (reg & (0x1F << shift)) >> shift;
189 step = abs(val - old);
193 reg = (reg & ~(0x1F << shift)) | (val << shift);
194 writel(reg, &anatop->reg_core);
197 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
205 static void imx_set_wdog_powerdown(bool enable)
207 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
208 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
210 /* Write to the PDE (Power Down Enable) bit */
211 writew(enable, &wdog1->wmcr);
212 writew(enable, &wdog2->wmcr);
215 static void set_ahb_rate(u32 val)
217 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
220 div = get_periph_clk() / val - 1;
221 reg = readl(&mxc_ccm->cbcdr);
223 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
224 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
227 static void clear_mmdc_ch_mask(void)
229 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
231 /* Clear MMDC channel mask */
232 writel(0, &mxc_ccm->ccdr);
235 int arch_cpu_init(void)
239 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
240 clear_mmdc_ch_mask();
243 * When low freq boot is enabled, ROM will not set AHB
244 * freq, so we need to ensure AHB freq is 132MHz in such
247 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
248 set_ahb_rate(132000000);
250 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
252 #ifdef CONFIG_APBH_DMA
260 int board_postclk_init(void)
262 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
267 #ifndef CONFIG_SYS_DCACHE_OFF
268 void enable_caches(void)
270 /* Avoid random hang when download by usb */
271 invalidate_dcache_all();
272 /* Enable D-cache. I-cache is already enabled in start.S */
277 #if defined(CONFIG_FEC_MXC)
278 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
280 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
281 struct fuse_bank *bank = &ocotp->bank[4];
282 struct fuse_bank4_regs *fuse =
283 (struct fuse_bank4_regs *)bank->fuse_regs;
285 u32 value = readl(&fuse->mac_addr_high);
286 mac[0] = (value >> 8);
289 value = readl(&fuse->mac_addr_low);
290 mac[2] = value >> 24 ;
291 mac[3] = value >> 16 ;
292 mac[4] = value >> 8 ;
298 void boot_mode_apply(unsigned cfg_val)
301 struct src *psrc = (struct src *)SRC_BASE_ADDR;
302 writel(cfg_val, &psrc->gpr9);
303 reg = readl(&psrc->gpr10);
308 writel(reg, &psrc->gpr10);
311 * cfg_val will be used for
312 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
313 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
314 * to SBMR1, which will determine the boot device.
316 const struct boot_mode soc_boot_modes[] = {
317 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
318 /* reserved value should start rom usb */
319 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
320 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
321 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
322 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
323 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
324 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
325 /* 4 bit bus width */
326 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
327 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
328 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
329 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
335 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
336 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
341 if (is_cpu_type(MXC_CPU_MX6SX))
344 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
345 * to make sure PFD is working right, otherwise, PFDs may
346 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
347 * workaround in ROM code, as bus clock need it
350 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
351 ANATOP_PFD_CLKGATE_MASK(1) |
352 ANATOP_PFD_CLKGATE_MASK(2) |
353 ANATOP_PFD_CLKGATE_MASK(3);
354 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
355 ANATOP_PFD_CLKGATE_MASK(1) |
356 ANATOP_PFD_CLKGATE_MASK(3);
359 * Don't reset PFD2 on DL/S
362 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
363 writel(mask480, &anatop->pfd_480_set);
364 writel(mask528, &anatop->pfd_528_set);
365 writel(mask480, &anatop->pfd_480_clr);
366 writel(mask528, &anatop->pfd_528_clr);
369 #ifdef CONFIG_IMX_HDMI
370 void imx_enable_hdmi_phy(void)
372 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
374 reg = readb(&hdmi->phy_conf0);
375 reg |= HDMI_PHY_CONF0_PDZ_MASK;
376 writeb(reg, &hdmi->phy_conf0);
378 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
379 writeb(reg, &hdmi->phy_conf0);
381 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
382 writeb(reg, &hdmi->phy_conf0);
383 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
386 void imx_setup_hdmi(void)
388 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
389 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
392 /* Turn on HDMI PHY clock */
393 reg = readl(&mxc_ccm->CCGR2);
394 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
395 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
396 writel(reg, &mxc_ccm->CCGR2);
397 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
398 reg = readl(&mxc_ccm->chsccdr);
399 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
400 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
401 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
402 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
403 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
404 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
405 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
406 writel(reg, &mxc_ccm->chsccdr);
410 #ifndef CONFIG_SYS_L2CACHE_OFF
411 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
412 void v7_outer_cache_enable(void)
414 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
417 #if defined CONFIG_MX6SL
418 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
419 val = readl(&iomux->gpr[11]);
420 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
421 /* L2 cache configured as OCRAM, reset it */
422 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
423 writel(val, &iomux->gpr[11]);
427 writel(0x132, &pl310->pl310_tag_latency_ctrl);
428 writel(0x132, &pl310->pl310_data_latency_ctrl);
430 val = readl(&pl310->pl310_prefetch_ctrl);
432 /* Turn on the L2 I/D prefetch */
436 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
437 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
438 * But according to ARM PL310 errata: 752271
439 * ID: 752271: Double linefill feature can cause data corruption
440 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
441 * Workaround: The only workaround to this erratum is to disable the
442 * double linefill feature. This is the default behavior.
448 writel(val, &pl310->pl310_prefetch_ctrl);
450 val = readl(&pl310->pl310_power_ctrl);
451 val |= L2X0_DYNAMIC_CLK_GATING_EN;
452 val |= L2X0_STNDBY_MODE_EN;
453 writel(val, &pl310->pl310_power_ctrl);
455 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
458 void v7_outer_cache_disable(void)
460 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
462 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
464 #endif /* !CONFIG_SYS_L2CACHE_OFF */