3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
38 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
39 u32 reg = readl(&anatop->digprog_sololite);
40 u32 type = ((reg >> 16) & 0xff);
42 if (type != MXC_CPU_MX6SL) {
43 reg = readl(&anatop->digprog);
44 type = ((reg >> 16) & 0xff);
45 if (type == MXC_CPU_MX6DL) {
46 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
47 u32 cfg = readl(&scu->config) & 3;
50 type = MXC_CPU_MX6SOLO;
53 reg &= 0xff; /* mx6 silicon revision */
54 return (type << 12) | (reg + 0x10);
57 #ifdef CONFIG_REVISION_TAG
58 u32 __weak get_board_rev(void)
60 u32 cpurev = get_cpu_rev();
61 u32 type = ((cpurev >> 12) & 0xff);
62 if (type == MXC_CPU_MX6SOLO)
63 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
71 struct aipstz_regs *aips1, *aips2;
73 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
74 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
77 * Set all MPROTx to be non-bufferable, trusted for R/W,
78 * not forced to user-mode.
80 writel(0x77777777, &aips1->mprot0);
81 writel(0x77777777, &aips1->mprot1);
82 writel(0x77777777, &aips2->mprot0);
83 writel(0x77777777, &aips2->mprot1);
86 * Set all OPACRx to be non-bufferable, not require
87 * supervisor privilege level for access,allow for
88 * write access and untrusted master access.
90 writel(0x00000000, &aips1->opacr0);
91 writel(0x00000000, &aips1->opacr1);
92 writel(0x00000000, &aips1->opacr2);
93 writel(0x00000000, &aips1->opacr3);
94 writel(0x00000000, &aips1->opacr4);
95 writel(0x00000000, &aips2->opacr0);
96 writel(0x00000000, &aips2->opacr1);
97 writel(0x00000000, &aips2->opacr2);
98 writel(0x00000000, &aips2->opacr3);
99 writel(0x00000000, &aips2->opacr4);
102 static void clear_ldo_ramp(void)
104 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
107 /* ROM may modify LDO ramp up time according to fuse setting, so in
108 * order to be in the safe side we neeed to reset these settings to
109 * match the reset value: 0'b00
111 reg = readl(&anatop->ana_misc2);
112 reg &= ~(0x3f << 24);
113 writel(reg, &anatop->ana_misc2);
119 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
120 * them to the specified millivolt level.
121 * Possible values are from 0.725V to 1.450V in steps of
124 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
126 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
127 u32 val, step, old, reg = readl(&anatop->reg_core);
131 val = 0x00; /* Power gated off */
133 val = 0x1F; /* Power FET switched full on. No regulation */
135 val = (mv - 700) / 25;
153 old = (reg & (0x1F << shift)) >> shift;
154 step = abs(val - old);
158 reg = (reg & ~(0x1F << shift)) | (val << shift);
159 writel(reg, &anatop->reg_core);
162 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
170 static void imx_set_wdog_powerdown(bool enable)
172 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
173 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
175 /* Write to the PDE (Power Down Enable) bit */
176 writew(enable, &wdog1->wmcr);
177 writew(enable, &wdog2->wmcr);
180 static void set_ahb_rate(u32 val)
182 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
185 div = get_periph_clk() / val - 1;
186 reg = readl(&mxc_ccm->cbcdr);
188 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
189 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
192 int arch_cpu_init(void)
197 * When low freq boot is enabled, ROM will not set AHB
198 * freq, so we need to ensure AHB freq is 132MHz in such
201 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
202 set_ahb_rate(132000000);
204 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
206 #ifdef CONFIG_APBH_DMA
214 int board_postclk_init(void)
216 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
221 #ifndef CONFIG_SYS_DCACHE_OFF
222 void enable_caches(void)
224 /* Avoid random hang when download by usb */
225 invalidate_dcache_all();
226 /* Enable D-cache. I-cache is already enabled in start.S */
231 #if defined(CONFIG_FEC_MXC)
232 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
234 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
235 struct fuse_bank *bank = &ocotp->bank[4];
236 struct fuse_bank4_regs *fuse =
237 (struct fuse_bank4_regs *)bank->fuse_regs;
239 u32 value = readl(&fuse->mac_addr_high);
240 mac[0] = (value >> 8);
243 value = readl(&fuse->mac_addr_low);
244 mac[2] = value >> 24 ;
245 mac[3] = value >> 16 ;
246 mac[4] = value >> 8 ;
252 void boot_mode_apply(unsigned cfg_val)
255 struct src *psrc = (struct src *)SRC_BASE_ADDR;
256 writel(cfg_val, &psrc->gpr9);
257 reg = readl(&psrc->gpr10);
262 writel(reg, &psrc->gpr10);
265 * cfg_val will be used for
266 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
267 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
268 * to SBMR1, which will determine the boot device.
270 const struct boot_mode soc_boot_modes[] = {
271 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
272 /* reserved value should start rom usb */
273 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
274 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
275 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
276 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
277 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
278 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
279 /* 4 bit bus width */
280 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
281 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
282 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
283 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
289 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
290 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
294 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
295 * to make sure PFD is working right, otherwise, PFDs may
296 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
297 * workaround in ROM code, as bus clock need it
300 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
301 ANATOP_PFD_CLKGATE_MASK(1) |
302 ANATOP_PFD_CLKGATE_MASK(2) |
303 ANATOP_PFD_CLKGATE_MASK(3);
304 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
305 ANATOP_PFD_CLKGATE_MASK(1) |
306 ANATOP_PFD_CLKGATE_MASK(3);
309 * Don't reset PFD2 on DL/S
312 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
313 writel(mask480, &anatop->pfd_480_set);
314 writel(mask528, &anatop->pfd_528_set);
315 writel(mask480, &anatop->pfd_480_clr);
316 writel(mask528, &anatop->pfd_528_clr);
319 #ifdef CONFIG_IMX_HDMI
320 void imx_enable_hdmi_phy(void)
322 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
324 reg = readb(&hdmi->phy_conf0);
325 reg |= HDMI_PHY_CONF0_PDZ_MASK;
326 writeb(reg, &hdmi->phy_conf0);
328 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
329 writeb(reg, &hdmi->phy_conf0);
331 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
332 writeb(reg, &hdmi->phy_conf0);
333 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
336 void imx_setup_hdmi(void)
338 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
339 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
342 /* Turn on HDMI PHY clock */
343 reg = readl(&mxc_ccm->CCGR2);
344 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
345 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
346 writel(reg, &mxc_ccm->CCGR2);
347 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
348 reg = readl(&mxc_ccm->chsccdr);
349 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
350 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
351 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
352 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
353 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
354 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
355 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
356 writel(reg, &mxc_ccm->chsccdr);