3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/sys_proto.h>
35 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
36 int reg = readl(&anatop->digprog);
38 /* Read mx6 variant: quad, dual or solo */
39 int system_rev = (reg >> 4) & 0xFF000;
40 /* Read mx6 silicon revision */
41 system_rev |= (reg & 0xFF) + 0x10;
46 #ifdef CONFIG_ARCH_CPU_INIT
49 struct aipstz_regs *aips1, *aips2;
51 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
52 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
55 * Set all MPROTx to be non-bufferable, trusted for R/W,
56 * not forced to user-mode.
58 writel(0x77777777, &aips1->mprot0);
59 writel(0x77777777, &aips1->mprot1);
60 writel(0x77777777, &aips2->mprot0);
61 writel(0x77777777, &aips2->mprot1);
64 * Set all OPACRx to be non-bufferable, not require
65 * supervisor privilege level for access,allow for
66 * write access and untrusted master access.
68 writel(0x00000000, &aips1->opacr0);
69 writel(0x00000000, &aips1->opacr1);
70 writel(0x00000000, &aips1->opacr2);
71 writel(0x00000000, &aips1->opacr3);
72 writel(0x00000000, &aips1->opacr4);
73 writel(0x00000000, &aips2->opacr0);
74 writel(0x00000000, &aips2->opacr1);
75 writel(0x00000000, &aips2->opacr2);
76 writel(0x00000000, &aips2->opacr3);
77 writel(0x00000000, &aips2->opacr4);
83 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
84 * them to the specified millivolt level.
85 * Possible values are from 0.725V to 1.450V in steps of
88 void set_vddsoc(u32 mv)
90 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
91 u32 val, reg = readl(&anatop->reg_core);
94 val = 0x00; /* Power gated off */
96 val = 0x1F; /* Power FET switched full on. No regulation */
98 val = (mv - 700) / 25;
101 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
102 * and set them to the calculated value (0.7V + val * 0.25V)
104 reg = (reg & ~(0x1F << 18)) | (val << 18);
105 writel(reg, &anatop->reg_core);
108 int arch_cpu_init(void)
112 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
118 #ifndef CONFIG_SYS_DCACHE_OFF
119 void enable_caches(void)
121 /* Enable D-cache. I-cache is already enabled in start.S */
126 #if defined(CONFIG_FEC_MXC)
127 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
129 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
130 struct fuse_bank *bank = &iim->bank[4];
131 struct fuse_bank4_regs *fuse =
132 (struct fuse_bank4_regs *)bank->fuse_regs;
134 u32 value = readl(&fuse->mac_addr_high);
135 mac[0] = (value >> 8);
138 value = readl(&fuse->mac_addr_low);
139 mac[2] = value >> 24 ;
140 mac[3] = value >> 16 ;
141 mac[4] = value >> 8 ;