3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/dma.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/bootm.h>
42 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
43 return readl(&scu->config) & 3;
48 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
49 u32 reg = readl(&anatop->digprog_sololite);
50 u32 type = ((reg >> 16) & 0xff);
52 if (type != MXC_CPU_MX6SL) {
53 reg = readl(&anatop->digprog);
54 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
55 u32 cfg = readl(&scu->config) & 3;
56 type = ((reg >> 16) & 0xff);
57 if (type == MXC_CPU_MX6DL) {
59 type = MXC_CPU_MX6SOLO;
62 if (type == MXC_CPU_MX6Q) {
68 reg &= 0xff; /* mx6 silicon revision */
69 return (type << 12) | (reg + 0x10);
72 #ifdef CONFIG_REVISION_TAG
73 u32 __weak get_board_rev(void)
75 u32 cpurev = get_cpu_rev();
76 u32 type = ((cpurev >> 12) & 0xff);
77 if (type == MXC_CPU_MX6SOLO)
78 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
80 if (type == MXC_CPU_MX6D)
81 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
89 struct aipstz_regs *aips1, *aips2;
91 struct aipstz_regs *aips3;
94 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
95 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
97 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
101 * Set all MPROTx to be non-bufferable, trusted for R/W,
102 * not forced to user-mode.
104 writel(0x77777777, &aips1->mprot0);
105 writel(0x77777777, &aips1->mprot1);
106 writel(0x77777777, &aips2->mprot0);
107 writel(0x77777777, &aips2->mprot1);
110 * Set all OPACRx to be non-bufferable, not require
111 * supervisor privilege level for access,allow for
112 * write access and untrusted master access.
114 writel(0x00000000, &aips1->opacr0);
115 writel(0x00000000, &aips1->opacr1);
116 writel(0x00000000, &aips1->opacr2);
117 writel(0x00000000, &aips1->opacr3);
118 writel(0x00000000, &aips1->opacr4);
119 writel(0x00000000, &aips2->opacr0);
120 writel(0x00000000, &aips2->opacr1);
121 writel(0x00000000, &aips2->opacr2);
122 writel(0x00000000, &aips2->opacr3);
123 writel(0x00000000, &aips2->opacr4);
127 * Set all MPROTx to be non-bufferable, trusted for R/W,
128 * not forced to user-mode.
130 writel(0x77777777, &aips3->mprot0);
131 writel(0x77777777, &aips3->mprot1);
134 * Set all OPACRx to be non-bufferable, not require
135 * supervisor privilege level for access,allow for
136 * write access and untrusted master access.
138 writel(0x00000000, &aips3->opacr0);
139 writel(0x00000000, &aips3->opacr1);
140 writel(0x00000000, &aips3->opacr2);
141 writel(0x00000000, &aips3->opacr3);
142 writel(0x00000000, &aips3->opacr4);
146 static void clear_ldo_ramp(void)
148 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
151 /* ROM may modify LDO ramp up time according to fuse setting, so in
152 * order to be in the safe side we neeed to reset these settings to
153 * match the reset value: 0'b00
155 reg = readl(&anatop->ana_misc2);
156 reg &= ~(0x3f << 24);
157 writel(reg, &anatop->ana_misc2);
161 * Set the PMU_REG_CORE register
163 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
164 * Possible values are from 0.725V to 1.450V in steps of
167 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
169 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
170 u32 val, step, old, reg = readl(&anatop->reg_core);
174 val = 0x00; /* Power gated off */
176 val = 0x1F; /* Power FET switched full on. No regulation */
178 val = (mv - 700) / 25;
196 old = (reg & (0x1F << shift)) >> shift;
197 step = abs(val - old);
201 reg = (reg & ~(0x1F << shift)) | (val << shift);
202 writel(reg, &anatop->reg_core);
205 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
213 static void imx_set_wdog_powerdown(bool enable)
215 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
216 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
218 /* Write to the PDE (Power Down Enable) bit */
219 writew(enable, &wdog1->wmcr);
220 writew(enable, &wdog2->wmcr);
223 static void set_ahb_rate(u32 val)
225 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
228 div = get_periph_clk() / val - 1;
229 reg = readl(&mxc_ccm->cbcdr);
231 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
232 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
235 static void clear_mmdc_ch_mask(void)
237 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
239 /* Clear MMDC channel mask */
240 writel(0, &mxc_ccm->ccdr);
243 int arch_cpu_init(void)
247 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
248 clear_mmdc_ch_mask();
251 * When low freq boot is enabled, ROM will not set AHB
252 * freq, so we need to ensure AHB freq is 132MHz in such
255 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
256 set_ahb_rate(132000000);
258 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
260 #ifdef CONFIG_APBH_DMA
268 int board_postclk_init(void)
270 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
275 #ifndef CONFIG_SYS_DCACHE_OFF
276 void enable_caches(void)
278 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
279 enum dcache_option option = DCACHE_WRITETHROUGH;
281 enum dcache_option option = DCACHE_WRITEBACK;
284 /* Avoid random hang when download by usb */
285 invalidate_dcache_all();
287 /* Enable D-cache. I-cache is already enabled in start.S */
290 /* Enable caching on OCRAM and ROM */
291 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
294 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
300 #if defined(CONFIG_FEC_MXC)
301 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
303 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
304 struct fuse_bank *bank = &ocotp->bank[4];
305 struct fuse_bank4_regs *fuse =
306 (struct fuse_bank4_regs *)bank->fuse_regs;
308 u32 value = readl(&fuse->mac_addr_high);
309 mac[0] = (value >> 8);
312 value = readl(&fuse->mac_addr_low);
313 mac[2] = value >> 24 ;
314 mac[3] = value >> 16 ;
315 mac[4] = value >> 8 ;
321 void boot_mode_apply(unsigned cfg_val)
324 struct src *psrc = (struct src *)SRC_BASE_ADDR;
325 writel(cfg_val, &psrc->gpr9);
326 reg = readl(&psrc->gpr10);
331 writel(reg, &psrc->gpr10);
334 * cfg_val will be used for
335 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
336 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
337 * to SBMR1, which will determine the boot device.
339 const struct boot_mode soc_boot_modes[] = {
340 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
341 /* reserved value should start rom usb */
342 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
343 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
344 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
345 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
346 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
347 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
348 /* 4 bit bus width */
349 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
350 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
351 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
352 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
358 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
359 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
362 u32 reg, periph1, periph2;
364 if (is_cpu_type(MXC_CPU_MX6SX))
367 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
368 * to make sure PFD is working right, otherwise, PFDs may
369 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
370 * workaround in ROM code, as bus clock need it
373 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
374 ANATOP_PFD_CLKGATE_MASK(1) |
375 ANATOP_PFD_CLKGATE_MASK(2) |
376 ANATOP_PFD_CLKGATE_MASK(3);
377 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
378 ANATOP_PFD_CLKGATE_MASK(3);
380 reg = readl(&ccm->cbcmr);
381 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
382 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
383 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
384 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
386 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
387 if ((periph2 != 0x2) && (periph1 != 0x2))
388 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
390 if ((periph2 != 0x1) && (periph1 != 0x1) &&
391 (periph2 != 0x3) && (periph1 != 0x3))
392 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
394 writel(mask480, &anatop->pfd_480_set);
395 writel(mask528, &anatop->pfd_528_set);
396 writel(mask480, &anatop->pfd_480_clr);
397 writel(mask528, &anatop->pfd_528_clr);
400 #ifdef CONFIG_IMX_HDMI
401 void imx_enable_hdmi_phy(void)
403 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
405 reg = readb(&hdmi->phy_conf0);
406 reg |= HDMI_PHY_CONF0_PDZ_MASK;
407 writeb(reg, &hdmi->phy_conf0);
409 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
410 writeb(reg, &hdmi->phy_conf0);
412 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
413 writeb(reg, &hdmi->phy_conf0);
414 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
417 void imx_setup_hdmi(void)
419 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
420 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
423 /* Turn on HDMI PHY clock */
424 reg = readl(&mxc_ccm->CCGR2);
425 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
426 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
427 writel(reg, &mxc_ccm->CCGR2);
428 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
429 reg = readl(&mxc_ccm->chsccdr);
430 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
431 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
432 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
433 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
434 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
435 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
436 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
437 writel(reg, &mxc_ccm->chsccdr);
441 #ifndef CONFIG_SYS_L2CACHE_OFF
442 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
443 void v7_outer_cache_enable(void)
445 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
448 #if defined CONFIG_MX6SL
449 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
450 val = readl(&iomux->gpr[11]);
451 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
452 /* L2 cache configured as OCRAM, reset it */
453 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
454 writel(val, &iomux->gpr[11]);
458 /* Must disable the L2 before changing the latency parameters */
459 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
461 writel(0x132, &pl310->pl310_tag_latency_ctrl);
462 writel(0x132, &pl310->pl310_data_latency_ctrl);
464 val = readl(&pl310->pl310_prefetch_ctrl);
466 /* Turn on the L2 I/D prefetch */
470 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
471 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
472 * But according to ARM PL310 errata: 752271
473 * ID: 752271: Double linefill feature can cause data corruption
474 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
475 * Workaround: The only workaround to this erratum is to disable the
476 * double linefill feature. This is the default behavior.
482 writel(val, &pl310->pl310_prefetch_ctrl);
484 val = readl(&pl310->pl310_power_ctrl);
485 val |= L2X0_DYNAMIC_CLK_GATING_EN;
486 val |= L2X0_STNDBY_MODE_EN;
487 writel(val, &pl310->pl310_power_ctrl);
489 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
492 void v7_outer_cache_disable(void)
494 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
496 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
498 #endif /* !CONFIG_SYS_L2CACHE_OFF */