3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/dma.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <imx_thermal.h>
41 #if defined(CONFIG_IMX6_THERMAL)
42 static const struct imx_thermal_plat imx6_thermal_plat = {
43 .regs = (void *)ANATOP_BASE_ADDR,
48 U_BOOT_DEVICE(imx6_thermal) = {
49 .name = "imx_thermal",
50 .platdata = &imx6_thermal_plat,
56 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
57 return readl(&scu->config) & 3;
62 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
63 u32 reg = readl(&anatop->digprog_sololite);
64 u32 type = ((reg >> 16) & 0xff);
67 if (type != MXC_CPU_MX6SL) {
68 reg = readl(&anatop->digprog);
69 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
70 u32 cfg = readl(&scu->config) & 3;
71 type = ((reg >> 16) & 0xff);
72 if (type == MXC_CPU_MX6DL) {
74 type = MXC_CPU_MX6SOLO;
77 if (type == MXC_CPU_MX6Q) {
83 major = ((reg >> 8) & 0xff);
84 reg &= 0xff; /* mx6 silicon revision */
85 return (type << 12) | (reg + (0x10 * (major + 1)));
89 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
90 * defines a 2-bit SPEED_GRADING
92 #define OCOTP_CFG3_SPEED_SHIFT 16
93 #define OCOTP_CFG3_SPEED_800MHZ 0
94 #define OCOTP_CFG3_SPEED_850MHZ 1
95 #define OCOTP_CFG3_SPEED_1GHZ 2
96 #define OCOTP_CFG3_SPEED_1P2GHZ 3
98 u32 get_cpu_speed_grade_hz(void)
100 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
101 struct fuse_bank *bank = &ocotp->bank[0];
102 struct fuse_bank0_regs *fuse =
103 (struct fuse_bank0_regs *)bank->fuse_regs;
106 val = readl(&fuse->cfg3);
107 val >>= OCOTP_CFG3_SPEED_SHIFT;
111 /* Valid for IMX6DQ */
112 case OCOTP_CFG3_SPEED_1P2GHZ:
113 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
115 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
116 case OCOTP_CFG3_SPEED_1GHZ:
118 /* Valid for IMX6DQ */
119 case OCOTP_CFG3_SPEED_850MHZ:
120 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
122 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
123 case OCOTP_CFG3_SPEED_800MHZ:
130 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
131 * defines a 2-bit Temperature Grade
133 * return temperature grade and min/max temperature in celcius
135 #define OCOTP_MEM0_TEMP_SHIFT 6
137 u32 get_cpu_temp_grade(int *minc, int *maxc)
139 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
140 struct fuse_bank *bank = &ocotp->bank[1];
141 struct fuse_bank1_regs *fuse =
142 (struct fuse_bank1_regs *)bank->fuse_regs;
145 val = readl(&fuse->mem0);
146 val >>= OCOTP_MEM0_TEMP_SHIFT;
150 if (val == TEMP_AUTOMOTIVE) {
153 } else if (val == TEMP_INDUSTRIAL) {
156 } else if (val == TEMP_EXTCOMMERCIAL) {
167 #ifdef CONFIG_REVISION_TAG
168 u32 __weak get_board_rev(void)
170 u32 cpurev = get_cpu_rev();
171 u32 type = ((cpurev >> 12) & 0xff);
172 if (type == MXC_CPU_MX6SOLO)
173 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
175 if (type == MXC_CPU_MX6D)
176 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
184 struct aipstz_regs *aips1, *aips2;
186 struct aipstz_regs *aips3;
189 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
190 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
192 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
196 * Set all MPROTx to be non-bufferable, trusted for R/W,
197 * not forced to user-mode.
199 writel(0x77777777, &aips1->mprot0);
200 writel(0x77777777, &aips1->mprot1);
201 writel(0x77777777, &aips2->mprot0);
202 writel(0x77777777, &aips2->mprot1);
205 * Set all OPACRx to be non-bufferable, not require
206 * supervisor privilege level for access,allow for
207 * write access and untrusted master access.
209 writel(0x00000000, &aips1->opacr0);
210 writel(0x00000000, &aips1->opacr1);
211 writel(0x00000000, &aips1->opacr2);
212 writel(0x00000000, &aips1->opacr3);
213 writel(0x00000000, &aips1->opacr4);
214 writel(0x00000000, &aips2->opacr0);
215 writel(0x00000000, &aips2->opacr1);
216 writel(0x00000000, &aips2->opacr2);
217 writel(0x00000000, &aips2->opacr3);
218 writel(0x00000000, &aips2->opacr4);
222 * Set all MPROTx to be non-bufferable, trusted for R/W,
223 * not forced to user-mode.
225 writel(0x77777777, &aips3->mprot0);
226 writel(0x77777777, &aips3->mprot1);
229 * Set all OPACRx to be non-bufferable, not require
230 * supervisor privilege level for access,allow for
231 * write access and untrusted master access.
233 writel(0x00000000, &aips3->opacr0);
234 writel(0x00000000, &aips3->opacr1);
235 writel(0x00000000, &aips3->opacr2);
236 writel(0x00000000, &aips3->opacr3);
237 writel(0x00000000, &aips3->opacr4);
241 static void clear_ldo_ramp(void)
243 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
246 /* ROM may modify LDO ramp up time according to fuse setting, so in
247 * order to be in the safe side we neeed to reset these settings to
248 * match the reset value: 0'b00
250 reg = readl(&anatop->ana_misc2);
251 reg &= ~(0x3f << 24);
252 writel(reg, &anatop->ana_misc2);
256 * Set the PMU_REG_CORE register
258 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
259 * Possible values are from 0.725V to 1.450V in steps of
262 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
264 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
265 u32 val, step, old, reg = readl(&anatop->reg_core);
269 val = 0x00; /* Power gated off */
271 val = 0x1F; /* Power FET switched full on. No regulation */
273 val = (mv - 700) / 25;
291 old = (reg & (0x1F << shift)) >> shift;
292 step = abs(val - old);
296 reg = (reg & ~(0x1F << shift)) | (val << shift);
297 writel(reg, &anatop->reg_core);
300 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
308 static void imx_set_wdog_powerdown(bool enable)
310 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
311 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
314 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
315 writew(enable, &wdog3->wmcr);
318 /* Write to the PDE (Power Down Enable) bit */
319 writew(enable, &wdog1->wmcr);
320 writew(enable, &wdog2->wmcr);
323 static void set_ahb_rate(u32 val)
325 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
328 div = get_periph_clk() / val - 1;
329 reg = readl(&mxc_ccm->cbcdr);
331 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
332 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
335 static void clear_mmdc_ch_mask(void)
337 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
339 /* Clear MMDC channel mask */
340 writel(0, &mxc_ccm->ccdr);
343 static void init_bandgap(void)
345 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
347 * Ensure the bandgap has stabilized.
349 while (!(readl(&anatop->ana_misc0) & 0x80))
352 * For best noise performance of the analog blocks using the
353 * outputs of the bandgap, the reftop_selfbiasoff bit should
356 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
361 static void set_preclk_from_osc(void)
363 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
366 reg = readl(&mxc_ccm->cscmr1);
367 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
368 writel(reg, &mxc_ccm->cscmr1);
372 #define SRC_SCR_WARM_RESET_ENABLE 0
374 static void init_src(void)
376 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
380 * force warm reset sources to generate cold reset
381 * for a more reliable restart
383 val = readl(&src_regs->scr);
384 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
385 writel(val, &src_regs->scr);
388 int arch_cpu_init(void)
392 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
393 clear_mmdc_ch_mask();
396 * Disable self-bias circuit in the analog bandap.
397 * The self-bias circuit is used by the bandgap during startup.
398 * This bit should be set after the bandgap has initialized.
403 * When low freq boot is enabled, ROM will not set AHB
404 * freq, so we need to ensure AHB freq is 132MHz in such
407 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
408 set_ahb_rate(132000000);
410 /* Set perclk to source from OSC 24MHz */
411 #if defined(CONFIG_MX6SL)
412 set_preclk_from_osc();
415 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
417 #ifdef CONFIG_APBH_DMA
427 int board_postclk_init(void)
429 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
434 #ifndef CONFIG_SYS_DCACHE_OFF
435 void enable_caches(void)
437 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
438 enum dcache_option option = DCACHE_WRITETHROUGH;
440 enum dcache_option option = DCACHE_WRITEBACK;
443 /* Avoid random hang when download by usb */
444 invalidate_dcache_all();
446 /* Enable D-cache. I-cache is already enabled in start.S */
449 /* Enable caching on OCRAM and ROM */
450 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
453 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
459 #if defined(CONFIG_FEC_MXC)
460 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
462 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
463 struct fuse_bank *bank = &ocotp->bank[4];
464 struct fuse_bank4_regs *fuse =
465 (struct fuse_bank4_regs *)bank->fuse_regs;
467 u32 value = readl(&fuse->mac_addr_high);
468 mac[0] = (value >> 8);
471 value = readl(&fuse->mac_addr_low);
472 mac[2] = value >> 24 ;
473 mac[3] = value >> 16 ;
474 mac[4] = value >> 8 ;
480 void boot_mode_apply(unsigned cfg_val)
483 struct src *psrc = (struct src *)SRC_BASE_ADDR;
484 writel(cfg_val, &psrc->gpr9);
485 reg = readl(&psrc->gpr10);
490 writel(reg, &psrc->gpr10);
493 * cfg_val will be used for
494 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
495 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
496 * instead of SBMR1 to determine the boot device.
498 const struct boot_mode soc_boot_modes[] = {
499 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
500 /* reserved value should start rom usb */
501 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
502 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
503 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
504 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
505 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
506 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
507 /* 4 bit bus width */
508 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
509 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
510 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
511 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
517 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
518 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
521 u32 reg, periph1, periph2;
523 if (is_cpu_type(MXC_CPU_MX6SX))
526 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
527 * to make sure PFD is working right, otherwise, PFDs may
528 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
529 * workaround in ROM code, as bus clock need it
532 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
533 ANATOP_PFD_CLKGATE_MASK(1) |
534 ANATOP_PFD_CLKGATE_MASK(2) |
535 ANATOP_PFD_CLKGATE_MASK(3);
536 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
537 ANATOP_PFD_CLKGATE_MASK(3);
539 reg = readl(&ccm->cbcmr);
540 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
541 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
542 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
543 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
545 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
546 if ((periph2 != 0x2) && (periph1 != 0x2))
547 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
549 if ((periph2 != 0x1) && (periph1 != 0x1) &&
550 (periph2 != 0x3) && (periph1 != 0x3))
551 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
553 writel(mask480, &anatop->pfd_480_set);
554 writel(mask528, &anatop->pfd_528_set);
555 writel(mask480, &anatop->pfd_480_clr);
556 writel(mask528, &anatop->pfd_528_clr);
559 #ifdef CONFIG_IMX_HDMI
560 void imx_enable_hdmi_phy(void)
562 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
564 reg = readb(&hdmi->phy_conf0);
565 reg |= HDMI_PHY_CONF0_PDZ_MASK;
566 writeb(reg, &hdmi->phy_conf0);
568 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
569 writeb(reg, &hdmi->phy_conf0);
571 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
572 writeb(reg, &hdmi->phy_conf0);
573 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
576 void imx_setup_hdmi(void)
578 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
579 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
582 /* Turn on HDMI PHY clock */
583 reg = readl(&mxc_ccm->CCGR2);
584 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
585 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
586 writel(reg, &mxc_ccm->CCGR2);
587 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
588 reg = readl(&mxc_ccm->chsccdr);
589 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
590 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
591 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
592 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
593 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
594 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
595 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
596 writel(reg, &mxc_ccm->chsccdr);
600 #ifndef CONFIG_SYS_L2CACHE_OFF
601 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
602 void v7_outer_cache_enable(void)
604 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
609 * Set bit 22 in the auxiliary control register. If this bit
610 * is cleared, PL310 treats Normal Shared Non-cacheable
611 * accesses as Cacheable no-allocate.
613 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
615 #if defined CONFIG_MX6SL
616 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
617 val = readl(&iomux->gpr[11]);
618 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
619 /* L2 cache configured as OCRAM, reset it */
620 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
621 writel(val, &iomux->gpr[11]);
625 /* Must disable the L2 before changing the latency parameters */
626 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
628 writel(0x132, &pl310->pl310_tag_latency_ctrl);
629 writel(0x132, &pl310->pl310_data_latency_ctrl);
631 val = readl(&pl310->pl310_prefetch_ctrl);
633 /* Turn on the L2 I/D prefetch */
637 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
638 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
639 * But according to ARM PL310 errata: 752271
640 * ID: 752271: Double linefill feature can cause data corruption
641 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
642 * Workaround: The only workaround to this erratum is to disable the
643 * double linefill feature. This is the default behavior.
649 writel(val, &pl310->pl310_prefetch_ctrl);
651 val = readl(&pl310->pl310_power_ctrl);
652 val |= L2X0_DYNAMIC_CLK_GATING_EN;
653 val |= L2X0_STNDBY_MODE_EN;
654 writel(val, &pl310->pl310_power_ctrl);
656 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
659 void v7_outer_cache_disable(void)
661 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
663 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
665 #endif /* !CONFIG_SYS_L2CACHE_OFF */