3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/dma.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <imx_thermal.h>
41 #if defined(CONFIG_IMX6_THERMAL)
42 static const struct imx_thermal_plat imx6_thermal_plat = {
43 .regs = (void *)ANATOP_BASE_ADDR,
48 U_BOOT_DEVICE(imx6_thermal) = {
49 .name = "imx_thermal",
50 .platdata = &imx6_thermal_plat,
56 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
57 return readl(&scu->config) & 3;
62 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
63 u32 reg = readl(&anatop->digprog_sololite);
64 u32 type = ((reg >> 16) & 0xff);
66 if (type != MXC_CPU_MX6SL) {
67 reg = readl(&anatop->digprog);
68 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
69 u32 cfg = readl(&scu->config) & 3;
70 type = ((reg >> 16) & 0xff);
71 if (type == MXC_CPU_MX6DL) {
73 type = MXC_CPU_MX6SOLO;
76 if (type == MXC_CPU_MX6Q) {
82 reg &= 0xff; /* mx6 silicon revision */
83 return (type << 12) | (reg + 0x10);
86 #ifdef CONFIG_REVISION_TAG
87 u32 __weak get_board_rev(void)
89 u32 cpurev = get_cpu_rev();
90 u32 type = ((cpurev >> 12) & 0xff);
91 if (type == MXC_CPU_MX6SOLO)
92 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
94 if (type == MXC_CPU_MX6D)
95 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
103 struct aipstz_regs *aips1, *aips2;
105 struct aipstz_regs *aips3;
108 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
109 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
111 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
115 * Set all MPROTx to be non-bufferable, trusted for R/W,
116 * not forced to user-mode.
118 writel(0x77777777, &aips1->mprot0);
119 writel(0x77777777, &aips1->mprot1);
120 writel(0x77777777, &aips2->mprot0);
121 writel(0x77777777, &aips2->mprot1);
124 * Set all OPACRx to be non-bufferable, not require
125 * supervisor privilege level for access,allow for
126 * write access and untrusted master access.
128 writel(0x00000000, &aips1->opacr0);
129 writel(0x00000000, &aips1->opacr1);
130 writel(0x00000000, &aips1->opacr2);
131 writel(0x00000000, &aips1->opacr3);
132 writel(0x00000000, &aips1->opacr4);
133 writel(0x00000000, &aips2->opacr0);
134 writel(0x00000000, &aips2->opacr1);
135 writel(0x00000000, &aips2->opacr2);
136 writel(0x00000000, &aips2->opacr3);
137 writel(0x00000000, &aips2->opacr4);
141 * Set all MPROTx to be non-bufferable, trusted for R/W,
142 * not forced to user-mode.
144 writel(0x77777777, &aips3->mprot0);
145 writel(0x77777777, &aips3->mprot1);
148 * Set all OPACRx to be non-bufferable, not require
149 * supervisor privilege level for access,allow for
150 * write access and untrusted master access.
152 writel(0x00000000, &aips3->opacr0);
153 writel(0x00000000, &aips3->opacr1);
154 writel(0x00000000, &aips3->opacr2);
155 writel(0x00000000, &aips3->opacr3);
156 writel(0x00000000, &aips3->opacr4);
160 static void clear_ldo_ramp(void)
162 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
165 /* ROM may modify LDO ramp up time according to fuse setting, so in
166 * order to be in the safe side we neeed to reset these settings to
167 * match the reset value: 0'b00
169 reg = readl(&anatop->ana_misc2);
170 reg &= ~(0x3f << 24);
171 writel(reg, &anatop->ana_misc2);
175 * Set the PMU_REG_CORE register
177 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
178 * Possible values are from 0.725V to 1.450V in steps of
181 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
183 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
184 u32 val, step, old, reg = readl(&anatop->reg_core);
188 val = 0x00; /* Power gated off */
190 val = 0x1F; /* Power FET switched full on. No regulation */
192 val = (mv - 700) / 25;
210 old = (reg & (0x1F << shift)) >> shift;
211 step = abs(val - old);
215 reg = (reg & ~(0x1F << shift)) | (val << shift);
216 writel(reg, &anatop->reg_core);
219 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
227 static void imx_set_wdog_powerdown(bool enable)
229 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
230 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
233 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
234 writew(enable, &wdog3->wmcr);
237 /* Write to the PDE (Power Down Enable) bit */
238 writew(enable, &wdog1->wmcr);
239 writew(enable, &wdog2->wmcr);
242 static void set_ahb_rate(u32 val)
244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
247 div = get_periph_clk() / val - 1;
248 reg = readl(&mxc_ccm->cbcdr);
250 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
251 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
254 static void clear_mmdc_ch_mask(void)
256 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
258 /* Clear MMDC channel mask */
259 writel(0, &mxc_ccm->ccdr);
262 static void init_bandgap(void)
264 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
266 * Ensure the bandgap has stabilized.
268 while (!(readl(&anatop->ana_misc0) & 0x80))
271 * For best noise performance of the analog blocks using the
272 * outputs of the bandgap, the reftop_selfbiasoff bit should
275 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
280 static void set_preclk_from_osc(void)
282 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
285 reg = readl(&mxc_ccm->cscmr1);
286 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
287 writel(reg, &mxc_ccm->cscmr1);
291 #define SRC_SCR_WARM_RESET_ENABLE 0
293 static void init_src(void)
295 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
299 * force warm reset sources to generate cold reset
300 * for a more reliable restart
302 val = readl(&src_regs->scr);
303 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
304 writel(val, &src_regs->scr);
307 int arch_cpu_init(void)
311 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
312 clear_mmdc_ch_mask();
315 * Disable self-bias circuit in the analog bandap.
316 * The self-bias circuit is used by the bandgap during startup.
317 * This bit should be set after the bandgap has initialized.
322 * When low freq boot is enabled, ROM will not set AHB
323 * freq, so we need to ensure AHB freq is 132MHz in such
326 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
327 set_ahb_rate(132000000);
329 /* Set perclk to source from OSC 24MHz */
330 #if defined(CONFIG_MX6SL)
331 set_preclk_from_osc();
334 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
336 #ifdef CONFIG_APBH_DMA
346 int board_postclk_init(void)
348 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
353 #ifndef CONFIG_SYS_DCACHE_OFF
354 void enable_caches(void)
356 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
357 enum dcache_option option = DCACHE_WRITETHROUGH;
359 enum dcache_option option = DCACHE_WRITEBACK;
362 /* Avoid random hang when download by usb */
363 invalidate_dcache_all();
365 /* Enable D-cache. I-cache is already enabled in start.S */
368 /* Enable caching on OCRAM and ROM */
369 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
372 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
378 #if defined(CONFIG_FEC_MXC)
379 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
381 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
382 struct fuse_bank *bank = &ocotp->bank[4];
383 struct fuse_bank4_regs *fuse =
384 (struct fuse_bank4_regs *)bank->fuse_regs;
386 u32 value = readl(&fuse->mac_addr_high);
387 mac[0] = (value >> 8);
390 value = readl(&fuse->mac_addr_low);
391 mac[2] = value >> 24 ;
392 mac[3] = value >> 16 ;
393 mac[4] = value >> 8 ;
399 void boot_mode_apply(unsigned cfg_val)
402 struct src *psrc = (struct src *)SRC_BASE_ADDR;
403 writel(cfg_val, &psrc->gpr9);
404 reg = readl(&psrc->gpr10);
409 writel(reg, &psrc->gpr10);
412 * cfg_val will be used for
413 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
414 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
415 * instead of SBMR1 to determine the boot device.
417 const struct boot_mode soc_boot_modes[] = {
418 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
419 /* reserved value should start rom usb */
420 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
421 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
422 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
423 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
424 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
425 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
426 /* 4 bit bus width */
427 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
428 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
429 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
430 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
436 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
437 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
440 u32 reg, periph1, periph2;
442 if (is_cpu_type(MXC_CPU_MX6SX))
445 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
446 * to make sure PFD is working right, otherwise, PFDs may
447 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
448 * workaround in ROM code, as bus clock need it
451 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
452 ANATOP_PFD_CLKGATE_MASK(1) |
453 ANATOP_PFD_CLKGATE_MASK(2) |
454 ANATOP_PFD_CLKGATE_MASK(3);
455 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
456 ANATOP_PFD_CLKGATE_MASK(3);
458 reg = readl(&ccm->cbcmr);
459 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
460 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
461 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
462 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
464 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
465 if ((periph2 != 0x2) && (periph1 != 0x2))
466 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
468 if ((periph2 != 0x1) && (periph1 != 0x1) &&
469 (periph2 != 0x3) && (periph1 != 0x3))
470 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
472 writel(mask480, &anatop->pfd_480_set);
473 writel(mask528, &anatop->pfd_528_set);
474 writel(mask480, &anatop->pfd_480_clr);
475 writel(mask528, &anatop->pfd_528_clr);
478 #ifdef CONFIG_IMX_HDMI
479 void imx_enable_hdmi_phy(void)
481 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
483 reg = readb(&hdmi->phy_conf0);
484 reg |= HDMI_PHY_CONF0_PDZ_MASK;
485 writeb(reg, &hdmi->phy_conf0);
487 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
488 writeb(reg, &hdmi->phy_conf0);
490 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
491 writeb(reg, &hdmi->phy_conf0);
492 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
495 void imx_setup_hdmi(void)
497 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
498 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
501 /* Turn on HDMI PHY clock */
502 reg = readl(&mxc_ccm->CCGR2);
503 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
504 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
505 writel(reg, &mxc_ccm->CCGR2);
506 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
507 reg = readl(&mxc_ccm->chsccdr);
508 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
509 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
510 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
511 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
512 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
513 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
514 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
515 writel(reg, &mxc_ccm->chsccdr);
519 #ifndef CONFIG_SYS_L2CACHE_OFF
520 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
521 void v7_outer_cache_enable(void)
523 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
528 * Set bit 22 in the auxiliary control register. If this bit
529 * is cleared, PL310 treats Normal Shared Non-cacheable
530 * accesses as Cacheable no-allocate.
532 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
534 #if defined CONFIG_MX6SL
535 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
536 val = readl(&iomux->gpr[11]);
537 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
538 /* L2 cache configured as OCRAM, reset it */
539 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
540 writel(val, &iomux->gpr[11]);
544 /* Must disable the L2 before changing the latency parameters */
545 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
547 writel(0x132, &pl310->pl310_tag_latency_ctrl);
548 writel(0x132, &pl310->pl310_data_latency_ctrl);
550 val = readl(&pl310->pl310_prefetch_ctrl);
552 /* Turn on the L2 I/D prefetch */
556 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
557 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
558 * But according to ARM PL310 errata: 752271
559 * ID: 752271: Double linefill feature can cause data corruption
560 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
561 * Workaround: The only workaround to this erratum is to disable the
562 * double linefill feature. This is the default behavior.
568 writel(val, &pl310->pl310_prefetch_ctrl);
570 val = readl(&pl310->pl310_power_ctrl);
571 val |= L2X0_DYNAMIC_CLK_GATING_EN;
572 val |= L2X0_STNDBY_MODE_EN;
573 writel(val, &pl310->pl310_power_ctrl);
575 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
578 void v7_outer_cache_disable(void)
580 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
582 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
584 #endif /* !CONFIG_SYS_L2CACHE_OFF */