2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/types.h>
10 #include <asm/arch/mx6-ddr.h>
11 #include <asm/arch/sys_proto.h>
13 #include <asm/types.h>
15 #if defined(CONFIG_MX6SX)
16 /* Configure MX6SX mmdc iomux */
17 void mx6sx_dram_iocfg(unsigned width,
18 const struct mx6sx_iomux_ddr_regs *ddr,
19 const struct mx6sx_iomux_grp_regs *grp)
21 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
22 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
24 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
25 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
28 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
29 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
32 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
35 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
36 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
37 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
40 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
41 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
42 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
43 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
44 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
45 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
46 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
49 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
50 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
51 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
53 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
54 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
58 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
59 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
60 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
62 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
63 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
65 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
66 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
68 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
69 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
74 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
75 /* Configure MX6DQ mmdc iomux */
76 void mx6dq_dram_iocfg(unsigned width,
77 const struct mx6dq_iomux_ddr_regs *ddr,
78 const struct mx6dq_iomux_grp_regs *grp)
80 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
81 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
83 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
84 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
87 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
88 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
91 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
92 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
95 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
96 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
97 mx6_grp_iomux->grp_addds = grp->grp_addds;
100 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
101 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
102 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
103 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
104 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
105 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
106 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
109 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
110 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
111 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
113 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
114 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
117 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
118 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
119 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
120 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
124 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
125 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
126 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
128 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
129 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
132 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
133 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
134 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
135 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
137 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
138 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
140 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
141 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
144 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
145 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
146 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
147 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
152 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
153 /* Configure MX6SDL mmdc iomux */
154 void mx6sdl_dram_iocfg(unsigned width,
155 const struct mx6sdl_iomux_ddr_regs *ddr,
156 const struct mx6sdl_iomux_grp_regs *grp)
158 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
159 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
161 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
162 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
165 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
166 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
169 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
170 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
173 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
174 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
175 mx6_grp_iomux->grp_addds = grp->grp_addds;
178 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
179 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
180 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
181 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
182 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
183 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
184 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
187 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
188 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
189 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
191 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
192 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
195 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
196 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
197 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
198 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
202 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
203 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
204 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
206 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
207 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
210 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
211 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
212 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
213 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
215 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
216 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
218 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
219 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
222 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
223 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
224 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
225 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
231 * Configure mx6 mmdc registers based on:
232 * - board-specific memory configuration
233 * - board-specific calibration data
234 * - ddr3 chip details
236 * The various calculations here are derived from the Freescale
237 * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
238 * configuration registers based on memory system and memory chip parameters.
240 * The defaults here are those which were specified in the spreadsheet.
241 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
242 * section titled MMDC initialization
244 #define MR(val, ba, cmd, cs1) \
245 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
247 #define MMDC1(entry, value) do {} while (0)
249 #define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
251 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
252 const struct mx6_mmdc_calibration *calib,
253 const struct mx6_ddr3_cfg *ddr3_cfg)
255 volatile struct mmdc_p_regs *mmdc0;
257 volatile struct mmdc_p_regs *mmdc1;
260 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
261 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
262 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
263 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
265 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
267 int clkper; /* clock period in picoseconds */
268 int clock; /* clock freq in MHz */
270 u16 mem_speed = ddr3_cfg->mem_speed;
272 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
274 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
277 /* Limit mem_speed for MX6D/MX6Q */
278 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
279 if (mem_speed > 1066)
280 mem_speed = 1066; /* 1066 MT/s */
284 /* Limit mem_speed for MX6S/MX6DL */
287 mem_speed = 800; /* 800 MT/s */
292 clock = mem_speed / 2;
294 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
295 * up to 528 MHz, so reduce the clock to fit chip specs
297 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
299 clock = 528; /* 528 MHz */
302 clkper = (1000 * 1000) / clock; /* pico seconds */
307 switch (ddr3_cfg->density) {
308 case 1: /* 1Gb per chip */
309 trfc = DIV_ROUND_UP(110000, clkper) - 1;
310 txs = DIV_ROUND_UP(120000, clkper) - 1;
312 case 2: /* 2Gb per chip */
313 trfc = DIV_ROUND_UP(160000, clkper) - 1;
314 txs = DIV_ROUND_UP(170000, clkper) - 1;
316 case 4: /* 4Gb per chip */
317 trfc = DIV_ROUND_UP(260000, clkper) - 1;
318 txs = DIV_ROUND_UP(270000, clkper) - 1;
320 case 8: /* 8Gb per chip */
321 trfc = DIV_ROUND_UP(350000, clkper) - 1;
322 txs = DIV_ROUND_UP(360000, clkper) - 1;
325 /* invalid density */
326 puts("invalid chip density\n");
334 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
335 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
336 if (ddr3_cfg->pagesz == 1) {
337 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
338 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
340 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
341 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
345 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
346 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
347 if (ddr3_cfg->pagesz == 1) {
348 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
349 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
351 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
352 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
356 txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
357 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
358 if (ddr3_cfg->pagesz == 1) {
359 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
360 trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
362 tfaw = DIV_ROUND_UP(45000, clkper) - 1;
363 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
367 txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
368 tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
369 if (ddr3_cfg->pagesz == 1) {
370 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
371 trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
373 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
374 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
378 puts("invalid memory speed\n");
382 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
383 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
384 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
387 twr = DIV_ROUND_UP(15000, clkper) - 1;
388 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
389 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
390 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
391 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
392 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
393 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
396 cs0_end = 4 * sysinfo->cs_density - 1;
398 debug("density:%d Gb (%d Gb per chip)\n",
399 sysinfo->cs_density, ddr3_cfg->density);
400 debug("clock: %dMHz (%d ps)\n", clock, clkper);
401 debug("memspd:%d\n", mem_speed);
402 debug("tcke=%d\n", tcke);
403 debug("tcksrx=%d\n", tcksrx);
404 debug("tcksre=%d\n", tcksre);
405 debug("taofpd=%d\n", taofpd);
406 debug("taonpd=%d\n", taonpd);
407 debug("todtlon=%d\n", todtlon);
408 debug("tanpd=%d\n", tanpd);
409 debug("taxpd=%d\n", taxpd);
410 debug("trfc=%d\n", trfc);
411 debug("txs=%d\n", txs);
412 debug("txp=%d\n", txp);
413 debug("txpdll=%d\n", txpdll);
414 debug("tfaw=%d\n", tfaw);
415 debug("tcl=%d\n", tcl);
416 debug("trcd=%d\n", trcd);
417 debug("trp=%d\n", trp);
418 debug("trc=%d\n", trc);
419 debug("tras=%d\n", tras);
420 debug("twr=%d\n", twr);
421 debug("tmrd=%d\n", tmrd);
422 debug("tcwl=%d\n", tcwl);
423 debug("tdllk=%d\n", tdllk);
424 debug("trtp=%d\n", trtp);
425 debug("twtr=%d\n", twtr);
426 debug("trrd=%d\n", trrd);
427 debug("txpr=%d\n", txpr);
428 debug("cs0_end=%d\n", cs0_end);
429 debug("ncs=%d\n", sysinfo->ncs);
430 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
431 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
432 debug("SRT=%d\n", ddr3_cfg->SRT);
433 debug("tcl=%d\n", tcl);
434 debug("twr=%d\n", twr);
437 * board-specific configuration:
438 * These values are determined empirically and vary per board layout
440 * appnote, ddr3 spreadsheet
442 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
443 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
444 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
445 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
446 mmdc0->mprddlctl = calib->p0_mprddlctl;
447 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
448 if (sysinfo->dsize > 1) {
449 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
450 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
451 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
452 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
453 MMDC1(mprddlctl, calib->p1_mprddlctl);
454 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
457 /* Read data DQ Byte0-3 delay */
458 mmdc0->mprddqby0dl = 0x33333333;
459 mmdc0->mprddqby1dl = 0x33333333;
460 if (sysinfo->dsize > 0) {
461 mmdc0->mprddqby2dl = 0x33333333;
462 mmdc0->mprddqby3dl = 0x33333333;
465 if (sysinfo->dsize > 1) {
466 MMDC1(mprddqby0dl, 0x33333333);
467 MMDC1(mprddqby1dl, 0x33333333);
468 MMDC1(mprddqby2dl, 0x33333333);
469 MMDC1(mprddqby3dl, 0x33333333);
472 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
473 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
474 mmdc0->mpodtctrl = val;
475 if (sysinfo->dsize > 1)
476 MMDC1(mpodtctrl, val);
478 /* complete calibration */
479 val = (1 << 11); /* Force measurement on delay-lines */
481 if (sysinfo->dsize > 1)
484 /* Step 1: configuration request */
485 mmdc0->mdscr = (u32)(1 << 15); /* config request */
487 /* Step 2: Timing configuration */
488 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
489 (txpdll << 9) | (tfaw << 4) | tcl;
490 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
491 (tras << 16) | (1 << 15) /* trpa */ |
492 (twr << 9) | (tmrd << 5) | tcwl;
493 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
494 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
495 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
496 mmdc0->mdasp = cs0_end; /* CS addressing */
498 /* Step 3: Configure DDR type */
499 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
500 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
501 (sysinfo->ralat << 6);
503 /* Step 4: Configure delay while leaving reset */
504 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
505 (sysinfo->rst_to_cke << 0);
507 /* Step 5: Configure DDR physical parameters (density and burst len) */
508 coladdr = ddr3_cfg->coladdr;
509 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
511 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
513 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
514 (coladdr - 9) << 20 | /* COL */
515 (1 << 19) | /* Burst Length = 8 for DDR3 */
516 (sysinfo->dsize << 16); /* DDR data bus size */
518 /* Step 6: Perform ZQ calibration */
519 val = 0xa1390001; /* one-time HW ZQ calib */
520 mmdc0->mpzqhwctrl = val;
521 if (sysinfo->dsize > 1)
522 MMDC1(mpzqhwctrl, val);
524 /* Step 7: Enable MMDC with desired chip select */
525 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
526 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
528 /* Step 8: Write Mode Registers to Init DDR3 devices */
529 for (cs = 0; cs < sysinfo->ncs; cs++) {
531 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
532 ((tcwl - 3) & 3) << 3;
533 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
534 mmdc0->mdscr = MR(val, 2, 3, cs);
536 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
537 mmdc0->mdscr = MR(0, 3, 3, cs);
539 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
540 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
541 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
542 mmdc0->mdscr = MR(val, 1, 3, cs);
544 val = ((tcl - 1) << 4) | /* CAS */
545 (1 << 8) | /* DLL Reset */
546 ((twr - 3) << 9); /* Write Recovery */
547 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
548 mmdc0->mdscr = MR(val, 0, 3, cs);
551 mmdc0->mdscr = MR(val, 0, 4, cs);
554 /* Step 10: Power down control and self-refresh */
555 mmdc0->mdpdc = (tcke & 0x7) << 16 |
556 5 << 12 | /* PWDT_1: 256 cycles */
557 5 << 8 | /* PWDT_0: 256 cycles */
558 1 << 6 | /* BOTH_CS_PD */
559 (tcksrx & 0x7) << 3 |
561 if (!sysinfo->pd_fast_exit)
562 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
563 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
565 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
567 mmdc0->mpzqhwctrl = val;
568 if (sysinfo->dsize > 1)
569 MMDC1(mpzqhwctrl, val);
571 /* Step 12: Configure and activate periodic refresh */
572 mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
573 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
575 /* Step 13: Deassert config request - init complete */
576 mmdc0->mdscr = 0x00000000;
578 /* wait for auto-ZQ calibration to complete */