2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
16 PLL_SYS, /* System PLL */
17 PLL_BUS, /* System Bus PLL*/
18 PLL_USBOTG, /* OTG USB PLL */
19 PLL_ENET, /* ENET PLL */
22 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
24 #ifdef CONFIG_MXC_OCOTP
25 void enable_ocotp_clk(unsigned char enable)
29 reg = __raw_readl(&imx_ccm->CCGR2);
31 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
33 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 __raw_writel(reg, &imx_ccm->CCGR2);
38 void enable_usboh3_clk(unsigned char enable)
42 reg = __raw_readl(&imx_ccm->CCGR6);
44 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
46 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
47 __raw_writel(reg, &imx_ccm->CCGR6);
51 #ifdef CONFIG_SYS_I2C_MXC
52 /* i2c_num can be from 0 - 2 */
53 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
61 mask = MXC_CCM_CCGR_CG_MASK
62 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
63 reg = __raw_readl(&imx_ccm->CCGR2);
68 __raw_writel(reg, &imx_ccm->CCGR2);
73 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
79 div = __raw_readl(&imx_ccm->analog_pll_sys);
80 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
82 return infreq * (div >> 1);
84 div = __raw_readl(&imx_ccm->analog_pll_528);
85 div &= BM_ANADIG_PLL_528_DIV_SELECT;
87 return infreq * (20 + (div << 1));
89 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
90 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
92 return infreq * (20 + (div << 1));
94 div = __raw_readl(&imx_ccm->analog_pll_enet);
95 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
97 return (div == 3 ? 125000000 : 25000000 * (div << 1));
104 static u32 get_mcu_main_clk(void)
108 reg = __raw_readl(&imx_ccm->cacrr);
109 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
110 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
111 freq = decode_pll(PLL_SYS, MXC_HCLK);
113 return freq / (reg + 1);
116 u32 get_periph_clk(void)
120 reg = __raw_readl(&imx_ccm->cbcdr);
121 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
122 reg = __raw_readl(&imx_ccm->cbcmr);
123 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
124 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
128 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
138 reg = __raw_readl(&imx_ccm->cbcmr);
139 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
140 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
144 freq = decode_pll(PLL_BUS, MXC_HCLK);
147 freq = PLL2_PFD2_FREQ;
150 freq = PLL2_PFD0_FREQ;
153 freq = PLL2_PFD2_DIV_FREQ;
163 static u32 get_ipg_clk(void)
167 reg = __raw_readl(&imx_ccm->cbcdr);
168 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
169 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
171 return get_ahb_clk() / (ipg_podf + 1);
174 static u32 get_ipg_per_clk(void)
176 u32 reg, perclk_podf;
178 reg = __raw_readl(&imx_ccm->cscmr1);
179 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
181 return get_ipg_clk() / (perclk_podf + 1);
184 static u32 get_uart_clk(void)
188 reg = __raw_readl(&imx_ccm->cscdr1);
190 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
193 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
194 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
196 return freq / (uart_podf + 1);
199 static u32 get_cspi_clk(void)
203 reg = __raw_readl(&imx_ccm->cscdr2);
204 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
205 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
207 return PLL3_60M / (cspi_podf + 1);
210 static u32 get_axi_clk(void)
212 u32 root_freq, axi_podf;
213 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
215 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
216 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
218 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
219 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
220 root_freq = PLL2_PFD2_FREQ;
222 root_freq = PLL3_PFD1_FREQ;
224 root_freq = get_periph_clk();
226 return root_freq / (axi_podf + 1);
229 static u32 get_emi_slow_clk(void)
231 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
233 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
234 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
235 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
236 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
237 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
239 switch (emi_clk_sel) {
241 root_freq = get_axi_clk();
244 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
247 root_freq = PLL2_PFD2_FREQ;
250 root_freq = PLL2_PFD0_FREQ;
254 return root_freq / (emi_slow_podf + 1);
258 static u32 get_mmdc_ch0_clk(void)
260 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
261 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
264 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
265 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
267 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
268 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
270 freq = decode_pll(PLL_BUS, MXC_HCLK);
273 freq = PLL2_PFD2_FREQ;
276 freq = PLL2_PFD0_FREQ;
279 freq = PLL2_PFD2_DIV_FREQ;
282 return freq / (podf + 1);
286 int enable_fec_anatop_clock(void)
289 s32 timeout = 100000;
291 struct anatop_regs __iomem *anatop =
292 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
294 reg = readl(&anatop->pll_enet);
295 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
296 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
297 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
298 writel(reg, &anatop->pll_enet);
300 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
307 /* Enable FEC clock */
308 reg |= BM_ANADIG_PLL_ENET_ENABLE;
309 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
310 writel(reg, &anatop->pll_enet);
316 static u32 get_mmdc_ch0_clk(void)
318 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
319 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
320 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
322 return get_periph_clk() / (mmdc_ch0_podf + 1);
326 static u32 get_usdhc_clk(u32 port)
328 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
329 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
330 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
334 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
335 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
336 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
340 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
341 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
342 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
346 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
347 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
348 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
352 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
353 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
354 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
362 root_freq = PLL2_PFD0_FREQ;
364 root_freq = PLL2_PFD2_FREQ;
366 return root_freq / (usdhc_podf + 1);
369 u32 imx_get_uartclk(void)
371 return get_uart_clk();
374 u32 imx_get_fecclk(void)
376 return decode_pll(PLL_ENET, MXC_HCLK);
379 int enable_sata_clock(void)
382 s32 timeout = 100000;
383 struct mxc_ccm_reg *const imx_ccm
384 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
386 /* Enable sata clock */
387 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
388 reg |= MXC_CCM_CCGR5_SATA_MASK;
389 writel(reg, &imx_ccm->CCGR5);
392 reg = readl(&imx_ccm->analog_pll_enet);
393 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
394 writel(reg, &imx_ccm->analog_pll_enet);
395 reg |= BM_ANADIG_PLL_SYS_ENABLE;
397 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
402 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
403 writel(reg, &imx_ccm->analog_pll_enet);
404 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
405 writel(reg, &imx_ccm->analog_pll_enet);
410 unsigned int mxc_get_clock(enum mxc_clock clk)
414 return get_mcu_main_clk();
416 return get_periph_clk();
418 return get_ahb_clk();
420 return get_ipg_clk();
423 return get_ipg_per_clk();
425 return get_uart_clk();
427 return get_cspi_clk();
429 return get_axi_clk();
430 case MXC_EMI_SLOW_CLK:
431 return get_emi_slow_clk();
433 return get_mmdc_ch0_clk();
435 return get_usdhc_clk(0);
437 return get_usdhc_clk(1);
439 return get_usdhc_clk(2);
441 return get_usdhc_clk(3);
443 return get_ahb_clk();
452 * Dump some core clockes.
454 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
457 freq = decode_pll(PLL_SYS, MXC_HCLK);
458 printf("PLL_SYS %8d MHz\n", freq / 1000000);
459 freq = decode_pll(PLL_BUS, MXC_HCLK);
460 printf("PLL_BUS %8d MHz\n", freq / 1000000);
461 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
462 printf("PLL_OTG %8d MHz\n", freq / 1000000);
463 freq = decode_pll(PLL_ENET, MXC_HCLK);
464 printf("PLL_NET %8d MHz\n", freq / 1000000);
467 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
468 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
469 #ifdef CONFIG_MXC_SPI
470 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
472 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
473 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
474 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
475 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
476 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
477 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
478 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
479 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
480 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
485 void enable_ipu_clock(void)
487 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
489 reg = readl(&mxc_ccm->CCGR3);
490 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
491 writel(reg, &mxc_ccm->CCGR3);
493 /***************************************************/
496 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,