2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
50 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
52 clrsetbits_le32(&imx_ccm->cs2cdr,
53 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
54 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
55 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
58 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 setbits_le32(&imx_ccm->CCGR4,
60 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
68 void enable_usboh3_clk(unsigned char enable)
72 reg = __raw_readl(&imx_ccm->CCGR6);
74 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
76 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
77 __raw_writel(reg, &imx_ccm->CCGR6);
81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
82 void enable_enet_clk(unsigned char enable)
84 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
87 setbits_le32(&imx_ccm->CCGR1, mask);
89 clrbits_le32(&imx_ccm->CCGR1, mask);
93 #ifdef CONFIG_MXC_UART
94 void enable_uart_clk(unsigned char enable)
96 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
99 setbits_le32(&imx_ccm->CCGR5, mask);
101 clrbits_le32(&imx_ccm->CCGR5, mask);
106 /* spi_num can be from 0 - 4 */
107 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
114 mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
116 setbits_le32(&imx_ccm->CCGR1, mask);
118 clrbits_le32(&imx_ccm->CCGR1, mask);
125 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
132 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
134 setbits_le32(&imx_ccm->CCGR6, mask);
136 clrbits_le32(&imx_ccm->CCGR6, mask);
142 #ifdef CONFIG_SYS_I2C_MXC
143 /* i2c_num can be from 0 - 3 */
144 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
152 mask = MXC_CCM_CCGR_CG_MASK
153 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
155 reg = __raw_readl(&imx_ccm->CCGR2);
160 __raw_writel(reg, &imx_ccm->CCGR2);
162 mask = MXC_CCM_CCGR_CG_MASK
163 << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
164 reg = __raw_readl(&imx_ccm->CCGR1);
169 __raw_writel(reg, &imx_ccm->CCGR1);
175 /* spi_num can be from 0 - SPI_MAX_NUM */
176 int enable_spi_clk(unsigned char enable, unsigned spi_num)
181 if (spi_num > SPI_MAX_NUM)
184 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
185 reg = __raw_readl(&imx_ccm->CCGR1);
190 __raw_writel(reg, &imx_ccm->CCGR1);
193 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
199 div = __raw_readl(&imx_ccm->analog_pll_sys);
200 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
202 return (infreq * div) >> 1;
204 div = __raw_readl(&imx_ccm->analog_pll_528);
205 div &= BM_ANADIG_PLL_528_DIV_SELECT;
207 return infreq * (20 + (div << 1));
209 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
210 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
212 return infreq * (20 + (div << 1));
214 div = __raw_readl(&imx_ccm->analog_pll_enet);
215 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
217 return 25000000 * (div + (div >> 1) + 1);
223 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
231 /* No PFD3 on PPL2 */
234 div = __raw_readl(&imx_ccm->analog_pfd_528);
235 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
238 div = __raw_readl(&imx_ccm->analog_pfd_480);
239 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
242 /* No PFD on other PLL */
246 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
247 ANATOP_PFD_FRAC_SHIFT(pfd_num));
250 static u32 get_mcu_main_clk(void)
254 reg = __raw_readl(&imx_ccm->cacrr);
255 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
256 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
257 freq = decode_pll(PLL_SYS, MXC_HCLK);
259 return freq / (reg + 1);
262 u32 get_periph_clk(void)
266 reg = __raw_readl(&imx_ccm->cbcdr);
267 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
268 reg = __raw_readl(&imx_ccm->cbcmr);
269 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
270 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
274 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
284 reg = __raw_readl(&imx_ccm->cbcmr);
285 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
286 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
290 freq = decode_pll(PLL_BUS, MXC_HCLK);
293 freq = mxc_get_pll_pfd(PLL_BUS, 2);
296 freq = mxc_get_pll_pfd(PLL_BUS, 0);
299 /* static / 2 divider */
300 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
310 static u32 get_ipg_clk(void)
314 reg = __raw_readl(&imx_ccm->cbcdr);
315 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
316 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
318 return get_ahb_clk() / (ipg_podf + 1);
321 static u32 get_ipg_per_clk(void)
323 u32 reg, perclk_podf;
325 reg = __raw_readl(&imx_ccm->cscmr1);
326 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
327 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
328 return MXC_HCLK; /* OSC 24Mhz */
330 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
332 return get_ipg_clk() / (perclk_podf + 1);
335 static u32 get_uart_clk(void)
338 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
339 reg = __raw_readl(&imx_ccm->cscdr1);
340 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
341 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
344 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
345 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
347 return freq / (uart_podf + 1);
350 static u32 get_cspi_clk(void)
354 reg = __raw_readl(&imx_ccm->cscdr2);
355 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
356 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
358 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
361 static u32 get_axi_clk(void)
363 u32 root_freq, axi_podf;
364 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
366 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
367 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
369 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
370 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
371 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
373 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
375 root_freq = get_periph_clk();
377 return root_freq / (axi_podf + 1);
380 static u32 get_emi_slow_clk(void)
382 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
384 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
385 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
386 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
387 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
388 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
390 switch (emi_clk_sel) {
392 root_freq = get_axi_clk();
395 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
398 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
401 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
405 return root_freq / (emi_slow_podf + 1);
408 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
409 static u32 get_mmdc_ch0_clk(void)
411 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
412 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
415 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
416 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
418 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
419 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
421 freq = decode_pll(PLL_BUS, MXC_HCLK);
424 freq = mxc_get_pll_pfd(PLL_BUS, 2);
427 freq = mxc_get_pll_pfd(PLL_BUS, 0);
430 /* static / 2 divider */
431 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
434 return freq / (podf + 1);
438 static u32 get_mmdc_ch0_clk(void)
440 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
441 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
442 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
444 return get_periph_clk() / (mmdc_ch0_podf + 1);
449 /* qspi_num can be from 0 - 1 */
450 void enable_qspi_clk(int qspi_num)
453 /* Enable QuadSPI clock */
456 /* disable the clock gate */
457 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
459 /* set 50M : (50 = 396 / 2 / 4) */
460 reg = readl(&imx_ccm->cscmr1);
461 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
462 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
463 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
464 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
465 writel(reg, &imx_ccm->cscmr1);
467 /* enable the clock gate */
468 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
472 * disable the clock gate
473 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
474 * disable both of them.
476 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
477 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
479 /* set 50M : (50 = 396 / 2 / 4) */
480 reg = readl(&imx_ccm->cs2cdr);
481 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
482 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
483 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
484 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
485 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
486 writel(reg, &imx_ccm->cs2cdr);
488 /*enable the clock gate*/
489 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
490 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
498 #ifdef CONFIG_FEC_MXC
499 int enable_fec_anatop_clock(enum enet_freq freq)
502 s32 timeout = 100000;
504 struct anatop_regs __iomem *anatop =
505 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
507 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
510 reg = readl(&anatop->pll_enet);
511 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
514 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
515 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
516 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
517 writel(reg, &anatop->pll_enet);
519 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
526 /* Enable FEC clock */
527 reg |= BM_ANADIG_PLL_ENET_ENABLE;
528 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
529 writel(reg, &anatop->pll_enet);
533 * Set enet ahb clock to 200MHz
534 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
536 reg = readl(&imx_ccm->chsccdr);
537 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
538 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
539 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
541 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
543 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
544 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
545 writel(reg, &imx_ccm->chsccdr);
547 /* Enable enet system clock */
548 reg = readl(&imx_ccm->CCGR3);
549 reg |= MXC_CCM_CCGR3_ENET_MASK;
550 writel(reg, &imx_ccm->CCGR3);
556 static u32 get_usdhc_clk(u32 port)
558 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
559 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
560 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
564 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
565 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
566 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
570 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
571 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
572 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
576 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
577 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
578 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
582 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
583 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
584 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
592 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
594 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
596 return root_freq / (usdhc_podf + 1);
599 u32 imx_get_uartclk(void)
601 return get_uart_clk();
604 u32 imx_get_fecclk(void)
606 return mxc_get_clock(MXC_IPG_CLK);
609 static int enable_enet_pll(uint32_t en)
611 struct mxc_ccm_reg *const imx_ccm
612 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
613 s32 timeout = 100000;
617 reg = readl(&imx_ccm->analog_pll_enet);
618 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
619 writel(reg, &imx_ccm->analog_pll_enet);
620 reg |= BM_ANADIG_PLL_SYS_ENABLE;
622 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
627 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
628 writel(reg, &imx_ccm->analog_pll_enet);
630 writel(reg, &imx_ccm->analog_pll_enet);
635 static void ungate_sata_clock(void)
637 struct mxc_ccm_reg *const imx_ccm =
638 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
640 /* Enable SATA clock. */
641 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
645 static void ungate_pcie_clock(void)
647 struct mxc_ccm_reg *const imx_ccm =
648 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
650 /* Enable PCIe clock. */
651 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
655 int enable_sata_clock(void)
658 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
661 void disable_sata_clock(void)
663 struct mxc_ccm_reg *const imx_ccm =
664 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
666 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
670 int enable_pcie_clock(void)
672 struct anatop_regs *anatop_regs =
673 (struct anatop_regs *)ANATOP_BASE_ADDR;
674 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
680 * The register ANATOP_MISC1 is not documented in the Freescale
681 * MX6RM. The register that is mapped in the ANATOP space and
682 * marked as ANATOP_MISC1 is actually documented in the PMU section
683 * of the datasheet as PMU_MISC1.
685 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
686 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
687 * for PCI express link that is clocked from the i.MX6.
689 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
690 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
691 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
692 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
693 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
695 if (is_cpu_type(MXC_CPU_MX6SX))
696 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
698 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
700 clrsetbits_le32(&anatop_regs->ana_misc1,
701 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
702 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
703 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
705 /* PCIe reference clock sourced from AXI. */
706 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
708 /* Party time! Ungate the clock to the PCIe. */
714 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
715 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
718 #ifdef CONFIG_SECURE_BOOT
719 void hab_caam_clock_enable(unsigned char enable)
723 /* CG4 ~ CG6, CAAM clocks */
724 reg = __raw_readl(&imx_ccm->CCGR0);
726 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
727 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
728 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
730 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
731 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
732 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
733 __raw_writel(reg, &imx_ccm->CCGR0);
736 reg = __raw_readl(&imx_ccm->CCGR6);
738 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
740 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
741 __raw_writel(reg, &imx_ccm->CCGR6);
745 static void enable_pll3(void)
747 struct anatop_regs __iomem *anatop =
748 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
750 /* make sure pll3 is enabled */
751 if ((readl(&anatop->usb1_pll_480_ctrl) &
752 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
753 /* enable pll's power */
754 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
755 &anatop->usb1_pll_480_ctrl_set);
756 writel(0x80, &anatop->ana_misc2_clr);
757 /* wait for pll lock */
758 while ((readl(&anatop->usb1_pll_480_ctrl) &
759 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
762 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
763 &anatop->usb1_pll_480_ctrl_clr);
764 /* enable pll output */
765 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
766 &anatop->usb1_pll_480_ctrl_set);
770 void enable_thermal_clk(void)
775 unsigned int mxc_get_clock(enum mxc_clock clk)
779 return get_mcu_main_clk();
781 return get_periph_clk();
783 return get_ahb_clk();
785 return get_ipg_clk();
788 return get_ipg_per_clk();
790 return get_uart_clk();
792 return get_cspi_clk();
794 return get_axi_clk();
795 case MXC_EMI_SLOW_CLK:
796 return get_emi_slow_clk();
798 return get_mmdc_ch0_clk();
800 return get_usdhc_clk(0);
802 return get_usdhc_clk(1);
804 return get_usdhc_clk(2);
806 return get_usdhc_clk(3);
808 return get_ahb_clk();
810 printf("Unsupported MXC CLK: %d\n", clk);
818 * Dump some core clockes.
820 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
823 freq = decode_pll(PLL_SYS, MXC_HCLK);
824 printf("PLL_SYS %8d MHz\n", freq / 1000000);
825 freq = decode_pll(PLL_BUS, MXC_HCLK);
826 printf("PLL_BUS %8d MHz\n", freq / 1000000);
827 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
828 printf("PLL_OTG %8d MHz\n", freq / 1000000);
829 freq = decode_pll(PLL_ENET, MXC_HCLK);
830 printf("PLL_NET %8d MHz\n", freq / 1000000);
833 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
834 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
835 #ifdef CONFIG_MXC_SPI
836 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
838 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
839 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
840 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
841 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
842 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
843 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
844 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
845 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
846 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
852 void enable_ipu_clock(void)
854 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
856 reg = readl(&mxc_ccm->CCGR3);
857 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
858 writel(reg, &mxc_ccm->CCGR3);
861 /***************************************************/
864 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,