2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
21 PLL_AUDIO, /* AUDIO PLL */
22 PLL_VIDEO, /* AUDIO PLL */
25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable)
32 reg = __raw_readl(&imx_ccm->CCGR2);
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
37 __raw_writel(reg, &imx_ccm->CCGR2);
41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg)
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm->CCGR4,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
55 clrsetbits_le32(&imx_ccm->cs2cdr,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
63 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
65 clrsetbits_le32(&imx_ccm->cs2cdr,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
71 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
73 setbits_le32(&imx_ccm->CCGR4,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
82 void enable_usboh3_clk(unsigned char enable)
86 reg = __raw_readl(&imx_ccm->CCGR6);
88 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
91 __raw_writel(reg, &imx_ccm->CCGR6);
95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
96 void enable_enet_clk(unsigned char enable)
101 mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
102 addr = &imx_ccm->CCGR0;
103 } else if (is_mx6ul()) {
104 mask = MXC_CCM_CCGR3_ENET_MASK;
105 addr = &imx_ccm->CCGR3;
107 mask = MXC_CCM_CCGR1_ENET_MASK;
108 addr = &imx_ccm->CCGR1;
112 setbits_le32(addr, mask);
114 clrbits_le32(addr, mask);
118 #ifdef CONFIG_MXC_UART
119 void enable_uart_clk(unsigned char enable)
123 if (is_mx6ul() || is_mx6ull())
124 mask = MXC_CCM_CCGR5_UART_MASK;
126 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
129 setbits_le32(&imx_ccm->CCGR5, mask);
131 clrbits_le32(&imx_ccm->CCGR5, mask);
136 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
143 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
145 setbits_le32(&imx_ccm->CCGR6, mask);
147 clrbits_le32(&imx_ccm->CCGR6, mask);
153 #ifdef CONFIG_SYS_I2C_MXC
154 /* i2c_num can be from 0 - 3 */
155 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
164 mask = MXC_CCM_CCGR_CG_MASK
165 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
167 reg = __raw_readl(&imx_ccm->CCGR2);
172 __raw_writel(reg, &imx_ccm->CCGR2);
174 if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
175 mask = MXC_CCM_CCGR6_I2C4_MASK;
176 addr = &imx_ccm->CCGR6;
178 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
179 addr = &imx_ccm->CCGR1;
181 reg = __raw_readl(addr);
186 __raw_writel(reg, addr);
192 /* spi_num can be from 0 - SPI_MAX_NUM */
193 int enable_spi_clk(unsigned char enable, unsigned spi_num)
198 if (spi_num > SPI_MAX_NUM)
201 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
202 reg = __raw_readl(&imx_ccm->CCGR1);
207 __raw_writel(reg, &imx_ccm->CCGR1);
210 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
212 u32 div, test_div, pll_num, pll_denom;
216 div = __raw_readl(&imx_ccm->analog_pll_sys);
217 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
219 return (infreq * div) >> 1;
221 div = __raw_readl(&imx_ccm->analog_pll_528);
222 div &= BM_ANADIG_PLL_528_DIV_SELECT;
224 return infreq * (20 + (div << 1));
226 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
227 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
229 return infreq * (20 + (div << 1));
231 div = __raw_readl(&imx_ccm->analog_pll_enet);
232 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
234 return 25000000 * (div + (div >> 1) + 1);
236 div = __raw_readl(&imx_ccm->analog_pll_audio);
237 if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
239 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
240 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
242 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
243 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
244 test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
245 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
246 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
248 debug("Error test_div\n");
251 test_div = 1 << (2 - test_div);
253 return infreq * (div + pll_num / pll_denom) / test_div;
255 div = __raw_readl(&imx_ccm->analog_pll_video);
256 if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
258 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
259 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
261 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
262 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
263 test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
264 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
265 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
267 debug("Error test_div\n");
270 test_div = 1 << (2 - test_div);
272 return infreq * (div + pll_num / pll_denom) / test_div;
278 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
285 if (!is_mx6ul() && !is_mx6ull()) {
287 /* No PFD3 on PLL2 */
291 div = __raw_readl(&imx_ccm->analog_pfd_528);
292 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
295 div = __raw_readl(&imx_ccm->analog_pfd_480);
296 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
299 /* No PFD on other PLL */
303 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
304 ANATOP_PFD_FRAC_SHIFT(pfd_num));
307 static u32 get_mcu_main_clk(void)
311 reg = __raw_readl(&imx_ccm->cacrr);
312 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
313 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
314 freq = decode_pll(PLL_SYS, MXC_HCLK);
316 return freq / (reg + 1);
319 u32 get_periph_clk(void)
321 u32 reg, div = 0, freq = 0;
323 reg = __raw_readl(&imx_ccm->cbcdr);
324 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
325 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
326 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
327 reg = __raw_readl(&imx_ccm->cbcmr);
328 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
329 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
333 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
343 reg = __raw_readl(&imx_ccm->cbcmr);
344 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
345 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
349 freq = decode_pll(PLL_BUS, MXC_HCLK);
352 freq = mxc_get_pll_pfd(PLL_BUS, 2);
355 freq = mxc_get_pll_pfd(PLL_BUS, 0);
358 /* static / 2 divider */
359 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
366 return freq / (div + 1);
369 static u32 get_ipg_clk(void)
373 reg = __raw_readl(&imx_ccm->cbcdr);
374 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
375 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
377 return get_ahb_clk() / (ipg_podf + 1);
380 static u32 get_ipg_per_clk(void)
382 u32 reg, perclk_podf;
384 reg = __raw_readl(&imx_ccm->cscmr1);
385 if (is_mx6sl() || is_mx6sx() ||
386 is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
387 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
388 return MXC_HCLK; /* OSC 24Mhz */
391 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
393 return get_ipg_clk() / (perclk_podf + 1);
396 static u32 get_uart_clk(void)
399 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
400 reg = __raw_readl(&imx_ccm->cscdr1);
402 if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
404 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
408 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
409 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
411 return freq / (uart_podf + 1);
414 static u32 get_cspi_clk(void)
418 reg = __raw_readl(&imx_ccm->cscdr2);
419 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
420 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
422 if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
424 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
425 return MXC_HCLK / (cspi_podf + 1);
428 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
431 static u32 get_axi_clk(void)
433 u32 root_freq, axi_podf;
434 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
436 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
437 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
439 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
440 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
441 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
443 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
445 root_freq = get_periph_clk();
447 return root_freq / (axi_podf + 1);
450 static u32 get_emi_slow_clk(void)
452 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
454 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
455 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
456 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
457 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
458 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
460 switch (emi_clk_sel) {
462 root_freq = get_axi_clk();
465 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
468 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
471 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
475 return root_freq / (emi_slow_podf + 1);
478 static u32 get_mmdc_ch0_clk(void)
480 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
481 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
483 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
485 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
486 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
487 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
488 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
489 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
490 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
492 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
495 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
497 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
498 freq = decode_pll(PLL_BUS, MXC_HCLK);
500 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
505 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
506 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
508 freq = decode_pll(PLL_BUS, MXC_HCLK);
511 freq = mxc_get_pll_pfd(PLL_BUS, 2);
514 freq = mxc_get_pll_pfd(PLL_BUS, 0);
517 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
518 switch (pmu_misc2_audio_div) {
521 pmu_misc2_audio_div = 1;
524 pmu_misc2_audio_div = 2;
527 pmu_misc2_audio_div = 4;
530 freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
535 return freq / (podf + 1) / (per2_clk2_podf + 1);
537 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
538 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
539 return get_periph_clk() / (podf + 1);
543 #if defined(CONFIG_VIDEO_MXS)
544 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
550 debug("pll5 div = %d, num = %d, denom = %d\n",
551 pll_div, pll_num, pll_denom);
553 /* Power up PLL5 video */
554 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
555 BM_ANADIG_PLL_VIDEO_BYPASS |
556 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
557 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
558 &imx_ccm->analog_pll_video_clr);
560 /* Set div, num and denom */
563 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
564 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
565 &imx_ccm->analog_pll_video_set);
568 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
569 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
570 &imx_ccm->analog_pll_video_set);
573 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
574 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
575 &imx_ccm->analog_pll_video_set);
578 puts("Wrong test_div!\n");
582 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
583 &imx_ccm->analog_pll_video_num);
584 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
585 &imx_ccm->analog_pll_video_denom);
588 start = get_timer(0); /* Get current timestamp */
591 reg = readl(&imx_ccm->analog_pll_video);
592 if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
594 writel(BM_ANADIG_PLL_VIDEO_ENABLE,
595 &imx_ccm->analog_pll_video_set);
598 } while (get_timer(0) < (start + 10)); /* Wait 10ms */
600 puts("Lock PLL5 timeout\n");
606 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
608 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
610 void mxs_set_lcdclk(u32 base_addr, u32 freq)
613 u32 hck = MXC_HCLK / 1000;
614 /* DIV_SELECT ranges from 27 to 54 */
618 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
619 u32 pll_div, pll_num, pll_denom, post_div = 1;
621 debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
623 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
624 debug("This chip not support lcd!\n");
628 if (base_addr == LCDIF1_BASE_ADDR) {
629 reg = readl(&imx_ccm->cscdr2);
630 /* Can't change clocks when clock not from pre-mux */
631 if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
636 reg = readl(&imx_ccm->cscdr2);
637 /* Can't change clocks when clock not from pre-mux */
638 if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
642 temp = freq * max_pred * max_postd;
645 * Register: PLL_VIDEO
646 * Bit Field: POST_DIV_SELECT
647 * 00 — Divide by 4.
648 * 01 — Divide by 2.
649 * 10 — Divide by 1.
651 * No need to check post_div(1)
653 for (post_div = 2; post_div <= 4; post_div <<= 1) {
654 if ((temp * post_div) > min) {
661 printf("Fail to set rate to %dkhz", freq);
666 /* Choose the best pred and postd to match freq for lcd */
667 for (i = 1; i <= max_pred; i++) {
668 for (j = 1; j <= max_postd; j++) {
670 if (temp > max || temp < min)
672 if (best == 0 || temp < best) {
681 printf("Fail to set rate to %dKHz", freq);
685 debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
687 pll_div = best / hck;
689 pll_num = (best - hck * pll_div) * pll_denom / hck;
693 * (24MHz * (pll_div + --------- ))
695 *freq KHz = --------------------------------
696 * post_div * pred * postd * 1000
699 if (base_addr == LCDIF1_BASE_ADDR) {
700 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
703 /* Select pre-lcd clock to PLL5 and set pre divider */
704 clrsetbits_le32(&imx_ccm->cscdr2,
705 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
706 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
707 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
709 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
711 /* Set the post divider */
712 clrsetbits_le32(&imx_ccm->cbcmr,
713 MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
715 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
716 } else if (is_mx6sx()) {
717 /* Setting LCDIF2 for i.MX6SX */
718 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
721 /* Select pre-lcd clock to PLL5 and set pre divider */
722 clrsetbits_le32(&imx_ccm->cscdr2,
723 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
724 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
725 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
727 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
729 /* Set the post divider */
730 clrsetbits_le32(&imx_ccm->cscmr1,
731 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
733 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
737 int enable_lcdif_clock(u32 base_addr)
740 u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
743 if ((base_addr != LCDIF1_BASE_ADDR) &&
744 (base_addr != LCDIF2_BASE_ADDR)) {
745 puts("Wrong LCD interface!\n");
748 /* Set to pre-mux clock at default */
749 lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
750 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
751 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
752 lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
753 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
754 MXC_CCM_CCGR3_DISP_AXI_MASK) :
755 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
756 MXC_CCM_CCGR3_DISP_AXI_MASK);
757 } else if (is_mx6ul() || is_mx6ull()) {
758 if (base_addr != LCDIF1_BASE_ADDR) {
759 puts("Wrong LCD interface!\n");
762 /* Set to pre-mux clock at default */
763 lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
764 lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
769 reg = readl(&imx_ccm->cscdr2);
770 reg &= ~lcdif_clk_sel_mask;
771 writel(reg, &imx_ccm->cscdr2);
773 /* Enable the LCDIF pix clock */
774 reg = readl(&imx_ccm->CCGR3);
775 reg |= lcdif_ccgr3_mask;
776 writel(reg, &imx_ccm->CCGR3);
778 reg = readl(&imx_ccm->CCGR2);
779 reg |= MXC_CCM_CCGR2_LCD_MASK;
780 writel(reg, &imx_ccm->CCGR2);
786 #ifdef CONFIG_FSL_QSPI
787 /* qspi_num can be from 0 - 1 */
788 void enable_qspi_clk(int qspi_num)
791 /* Enable QuadSPI clock */
794 /* disable the clock gate */
795 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
797 /* set 50M : (50 = 396 / 2 / 4) */
798 reg = readl(&imx_ccm->cscmr1);
799 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
800 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
801 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
802 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
803 writel(reg, &imx_ccm->cscmr1);
805 /* enable the clock gate */
806 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
810 * disable the clock gate
811 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
812 * disable both of them.
814 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
815 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
817 /* set 50M : (50 = 396 / 2 / 4) */
818 reg = readl(&imx_ccm->cs2cdr);
819 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
820 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
821 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
822 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
823 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
824 writel(reg, &imx_ccm->cs2cdr);
826 /*enable the clock gate*/
827 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
828 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
836 #ifdef CONFIG_FEC_MXC
837 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
840 s32 timeout = 100000;
842 struct anatop_regs __iomem *anatop =
843 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
845 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
848 reg = readl(&anatop->pll_enet);
851 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
852 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
853 } else if (fec_id == 1) {
854 /* Only i.MX6SX/UL support ENET2 */
855 if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
857 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
858 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
863 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
864 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
865 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
866 writel(reg, &anatop->pll_enet);
868 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
875 /* Enable FEC clock */
877 reg |= BM_ANADIG_PLL_ENET_ENABLE;
879 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
880 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
881 writel(reg, &anatop->pll_enet);
884 /* Disable enet system clcok before switching clock parent */
885 reg = readl(&imx_ccm->CCGR3);
886 reg &= ~MXC_CCM_CCGR3_ENET_MASK;
887 writel(reg, &imx_ccm->CCGR3);
890 * Set enet ahb clock to 200MHz
891 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
893 reg = readl(&imx_ccm->chsccdr);
894 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
895 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
896 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
898 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
900 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
901 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
902 writel(reg, &imx_ccm->chsccdr);
904 /* Enable enet system clock */
905 reg = readl(&imx_ccm->CCGR3);
906 reg |= MXC_CCM_CCGR3_ENET_MASK;
907 writel(reg, &imx_ccm->CCGR3);
913 static u32 get_usdhc_clk(u32 port)
915 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
916 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
917 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
921 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
922 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
923 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
927 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
928 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
929 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
933 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
934 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
935 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
939 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
940 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
941 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
949 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
951 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
953 return root_freq / (usdhc_podf + 1);
956 u32 imx_get_uartclk(void)
958 return get_uart_clk();
961 u32 imx_get_fecclk(void)
963 return mxc_get_clock(MXC_IPG_CLK);
966 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
967 static int enable_enet_pll(uint32_t en)
969 struct mxc_ccm_reg *const imx_ccm
970 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
971 s32 timeout = 100000;
975 reg = readl(&imx_ccm->analog_pll_enet);
976 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
977 writel(reg, &imx_ccm->analog_pll_enet);
978 reg |= BM_ANADIG_PLL_SYS_ENABLE;
980 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
985 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
986 writel(reg, &imx_ccm->analog_pll_enet);
988 writel(reg, &imx_ccm->analog_pll_enet);
993 #ifdef CONFIG_CMD_SATA
994 static void ungate_sata_clock(void)
996 struct mxc_ccm_reg *const imx_ccm =
997 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
999 /* Enable SATA clock. */
1000 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1003 int enable_sata_clock(void)
1005 ungate_sata_clock();
1006 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
1009 void disable_sata_clock(void)
1011 struct mxc_ccm_reg *const imx_ccm =
1012 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1014 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
1018 #ifdef CONFIG_PCIE_IMX
1019 static void ungate_pcie_clock(void)
1021 struct mxc_ccm_reg *const imx_ccm =
1022 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1024 /* Enable PCIe clock. */
1025 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
1028 int enable_pcie_clock(void)
1030 struct anatop_regs *anatop_regs =
1031 (struct anatop_regs *)ANATOP_BASE_ADDR;
1032 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1038 * The register ANATOP_MISC1 is not documented in the Freescale
1039 * MX6RM. The register that is mapped in the ANATOP space and
1040 * marked as ANATOP_MISC1 is actually documented in the PMU section
1041 * of the datasheet as PMU_MISC1.
1043 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1044 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1045 * for PCI express link that is clocked from the i.MX6.
1047 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1048 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1049 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1050 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1051 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1054 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1056 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1058 clrsetbits_le32(&anatop_regs->ana_misc1,
1059 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1060 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1061 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1063 /* PCIe reference clock sourced from AXI. */
1064 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1066 /* Party time! Ungate the clock to the PCIe. */
1067 #ifdef CONFIG_CMD_SATA
1068 ungate_sata_clock();
1070 ungate_pcie_clock();
1072 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1073 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1077 #ifdef CONFIG_SECURE_BOOT
1078 void hab_caam_clock_enable(unsigned char enable)
1083 /* CG5, DCP clock */
1084 reg = __raw_readl(&imx_ccm->CCGR0);
1086 reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
1088 reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
1089 __raw_writel(reg, &imx_ccm->CCGR0);
1091 /* CG4 ~ CG6, CAAM clocks */
1092 reg = __raw_readl(&imx_ccm->CCGR0);
1094 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1095 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1096 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1098 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1099 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1100 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1101 __raw_writel(reg, &imx_ccm->CCGR0);
1105 reg = __raw_readl(&imx_ccm->CCGR6);
1107 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1109 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1110 __raw_writel(reg, &imx_ccm->CCGR6);
1114 static void enable_pll3(void)
1116 struct anatop_regs __iomem *anatop =
1117 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1119 /* make sure pll3 is enabled */
1120 if ((readl(&anatop->usb1_pll_480_ctrl) &
1121 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1122 /* enable pll's power */
1123 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1124 &anatop->usb1_pll_480_ctrl_set);
1125 writel(0x80, &anatop->ana_misc2_clr);
1126 /* wait for pll lock */
1127 while ((readl(&anatop->usb1_pll_480_ctrl) &
1128 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1130 /* disable bypass */
1131 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1132 &anatop->usb1_pll_480_ctrl_clr);
1133 /* enable pll output */
1134 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1135 &anatop->usb1_pll_480_ctrl_set);
1139 void enable_thermal_clk(void)
1144 unsigned int mxc_get_clock(enum mxc_clock clk)
1148 return get_mcu_main_clk();
1150 return get_periph_clk();
1152 return get_ahb_clk();
1154 return get_ipg_clk();
1155 case MXC_IPG_PERCLK:
1157 return get_ipg_per_clk();
1159 return get_uart_clk();
1161 return get_cspi_clk();
1163 return get_axi_clk();
1164 case MXC_EMI_SLOW_CLK:
1165 return get_emi_slow_clk();
1167 return get_mmdc_ch0_clk();
1169 return get_usdhc_clk(0);
1170 case MXC_ESDHC2_CLK:
1171 return get_usdhc_clk(1);
1172 case MXC_ESDHC3_CLK:
1173 return get_usdhc_clk(2);
1174 case MXC_ESDHC4_CLK:
1175 return get_usdhc_clk(3);
1177 return get_ahb_clk();
1179 printf("Unsupported MXC CLK: %d\n", clk);
1187 * Dump some core clockes.
1189 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1192 freq = decode_pll(PLL_SYS, MXC_HCLK);
1193 printf("PLL_SYS %8d MHz\n", freq / 1000000);
1194 freq = decode_pll(PLL_BUS, MXC_HCLK);
1195 printf("PLL_BUS %8d MHz\n", freq / 1000000);
1196 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1197 printf("PLL_OTG %8d MHz\n", freq / 1000000);
1198 freq = decode_pll(PLL_ENET, MXC_HCLK);
1199 printf("PLL_NET %8d MHz\n", freq / 1000000);
1202 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000);
1203 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1204 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1205 #ifdef CONFIG_MXC_SPI
1206 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1208 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1209 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1210 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1211 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1212 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1213 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1214 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
1215 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
1216 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
1221 #ifndef CONFIG_MX6SX
1222 void enable_ipu_clock(void)
1224 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1226 reg = readl(&mxc_ccm->CCGR3);
1227 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1228 writel(reg, &mxc_ccm->CCGR3);
1231 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1232 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1237 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1238 defined(CONFIG_MX6S)
1239 static void disable_ldb_di_clock_sources(void)
1241 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1244 /* Make sure PFDs are disabled at boot. */
1245 reg = readl(&mxc_ccm->analog_pfd_528);
1246 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1251 writel(reg, &mxc_ccm->analog_pfd_528);
1253 /* Disable PLL3 PFDs */
1254 reg = readl(&mxc_ccm->analog_pfd_480);
1256 writel(reg, &mxc_ccm->analog_pfd_480);
1259 reg = readl(&mxc_ccm->analog_pll_video);
1261 writel(reg, &mxc_ccm->analog_pll_video);
1264 static void enable_ldb_di_clock_sources(void)
1266 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1269 reg = readl(&mxc_ccm->analog_pfd_528);
1271 reg &= ~(0x80008080);
1273 reg &= ~(0x80808080);
1274 writel(reg, &mxc_ccm->analog_pfd_528);
1276 reg = readl(&mxc_ccm->analog_pfd_480);
1277 reg &= ~(0x80808080);
1278 writel(reg, &mxc_ccm->analog_pfd_480);
1282 * Try call this function as early in the boot process as possible since the
1283 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1285 void select_ldb_di_clock_source(enum ldb_di_clock clk)
1287 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1291 * Need to follow a strict procedure when changing the LDB
1292 * clock, else we can introduce a glitch. Things to keep in
1294 * 1. The current and new parent clocks must be disabled.
1295 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1297 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1298 * the top four options are in one mux and the PLL3 option along
1299 * with another option is in the second mux. There is third mux
1300 * used to decide between the first and second mux.
1301 * The code below switches the parent to the bottom mux first
1302 * and then manipulates the top mux. This ensures that no glitch
1303 * will enter the divider.
1305 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1306 * for this clock. The only way to disable this clock is to move
1307 * it to pll3_sw_clk and then to disable pll3_sw_clk
1308 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1311 /* Disable all ldb_di clock parents */
1312 disable_ldb_di_clock_sources();
1314 /* Set MMDC_CH1 mask bit */
1315 reg = readl(&mxc_ccm->ccdr);
1316 reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1317 writel(reg, &mxc_ccm->ccdr);
1319 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1320 reg = readl(&mxc_ccm->cbcmr);
1321 reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
1322 writel(reg, &mxc_ccm->cbcmr);
1325 * Set the periph2_clk_sel to the top mux so that
1326 * mmdc_ch1 is from pll3_sw_clk.
1328 reg = readl(&mxc_ccm->cbcdr);
1329 reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1330 writel(reg, &mxc_ccm->cbcdr);
1332 /* Wait for the clock switch */
1333 while (readl(&mxc_ccm->cdhipr))
1335 /* Disable pll3_sw_clk by selecting bypass clock source */
1336 reg = readl(&mxc_ccm->ccsr);
1337 reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1338 writel(reg, &mxc_ccm->ccsr);
1340 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1341 reg = readl(&mxc_ccm->cs2cdr);
1342 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1343 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1344 writel(reg, &mxc_ccm->cs2cdr);
1346 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1347 reg = readl(&mxc_ccm->cs2cdr);
1348 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1349 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1350 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1351 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1352 writel(reg, &mxc_ccm->cs2cdr);
1354 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1355 reg = readl(&mxc_ccm->cs2cdr);
1356 reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1357 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
1358 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
1359 | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
1360 writel(reg, &mxc_ccm->cs2cdr);
1362 /* Unbypass pll3_sw_clk */
1363 reg = readl(&mxc_ccm->ccsr);
1364 reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
1365 writel(reg, &mxc_ccm->ccsr);
1368 * Set the periph2_clk_sel back to the bottom mux so that
1369 * mmdc_ch1 is from its original parent.
1371 reg = readl(&mxc_ccm->cbcdr);
1372 reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
1373 writel(reg, &mxc_ccm->cbcdr);
1375 /* Wait for the clock switch */
1376 while (readl(&mxc_ccm->cdhipr))
1378 /* Clear MMDC_CH1 mask bit */
1379 reg = readl(&mxc_ccm->ccdr);
1380 reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
1381 writel(reg, &mxc_ccm->ccdr);
1383 enable_ldb_di_clock_sources();
1387 #ifndef CONFIG_SYS_NO_FLASH
1388 void enable_eim_clk(unsigned char enable)
1392 reg = __raw_readl(&imx_ccm->CCGR6);
1394 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1396 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1397 __raw_writel(reg, &imx_ccm->CCGR6);
1401 /***************************************************/
1404 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,