3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/errno.h>
17 #include <asm/imx-common/boot_mode.h>
19 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
20 #error "CPU_TYPE not defined"
26 int system_rev = 0x51000;
28 int system_rev = 0x53000;
30 int reg = __raw_readl(ROM_SI_REV);
32 #if defined(CONFIG_MX51)
35 system_rev |= CHIP_REV_1_1;
38 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
39 system_rev |= CHIP_REV_2_5;
41 system_rev |= CHIP_REV_2_0;
44 system_rev |= CHIP_REV_3_0;
47 system_rev |= CHIP_REV_1_0;
52 system_rev |= CHIP_REV_1_0;
59 #ifdef CONFIG_REVISION_TAG
60 u32 __weak get_board_rev(void)
66 #ifndef CONFIG_SYS_DCACHE_OFF
67 void enable_caches(void)
69 /* Enable D-cache. I-cache is already enabled in start.S */
74 #if defined(CONFIG_FEC_MXC)
75 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
78 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
79 struct fuse_bank *bank = &iim->bank[1];
80 struct fuse_bank1_regs *fuse =
81 (struct fuse_bank1_regs *)bank->fuse_regs;
83 for (i = 0; i < 6; i++)
84 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
88 void set_chipselect_size(int const cs_size)
91 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
92 reg = readl(&iomuxc_regs->gpr1);
96 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
100 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
103 case CS0_64M_CS1_32M_CS2_32M:
104 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
107 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
108 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
112 printf("Unknown chip select size: %d\n", cs_size);
116 writel(reg, &iomuxc_regs->gpr1);
120 void boot_mode_apply(unsigned cfg_val)
122 writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
125 * cfg_val will be used for
126 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
128 * If bit 28 of LPGR is set upon watchdog reset,
129 * bits[25:0] of LPGR will move to SBMR.
131 const struct boot_mode soc_boot_modes[] = {
132 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
133 /* usb or serial download */
134 {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
135 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
136 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
137 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
138 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
139 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
140 /* 4 bit bus width */
141 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
142 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
143 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
144 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},