3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
31 #include <asm/errno.h>
33 #include <asm/imx-common/boot_mode.h>
35 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
36 #error "CPU_TYPE not defined"
42 int system_rev = 0x51000;
44 int system_rev = 0x53000;
46 int reg = __raw_readl(ROM_SI_REV);
48 #if defined(CONFIG_MX51)
51 system_rev |= CHIP_REV_1_1;
54 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
55 system_rev |= CHIP_REV_2_5;
57 system_rev |= CHIP_REV_2_0;
60 system_rev |= CHIP_REV_3_0;
63 system_rev |= CHIP_REV_1_0;
68 system_rev |= CHIP_REV_1_0;
75 #ifndef CONFIG_SYS_DCACHE_OFF
76 void enable_caches(void)
78 /* Enable D-cache. I-cache is already enabled in start.S */
83 #if defined(CONFIG_FEC_MXC)
84 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
87 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
88 struct fuse_bank *bank = &iim->bank[1];
89 struct fuse_bank1_regs *fuse =
90 (struct fuse_bank1_regs *)bank->fuse_regs;
92 for (i = 0; i < 6; i++)
93 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
97 void set_chipselect_size(int const cs_size)
100 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
101 reg = readl(&iomuxc_regs->gpr1);
105 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
108 case CS0_64M_CS1_64M:
109 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
112 case CS0_64M_CS1_32M_CS2_32M:
113 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
116 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
117 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
121 printf("Unknown chip select size: %d\n", cs_size);
125 writel(reg, &iomuxc_regs->gpr1);
129 void boot_mode_apply(unsigned cfg_val)
131 writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
134 * cfg_val will be used for
135 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
137 * If bit 28 of LPGR is set upon watchdog reset,
138 * bits[25:0] of LPGR will move to SBMR.
140 const struct boot_mode soc_boot_modes[] = {
141 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
142 /* usb or serial download */
143 {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
144 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
145 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
146 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
147 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
148 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
149 /* 4 bit bus width */
150 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
151 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
152 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
153 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},