2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/asm-offsets.h>
27 * L2CC Cache setup/invalidation/disable
30 /* explicitly disable L2 cache */
31 mrc 15, 0, r0, c1, c0, 1
33 mcr 15, 0, r0, c1, c0, 1
35 /* reconfigure L2 cache aux control reg */
36 mov r0, #0xC0 /* tag RAM */
37 add r0, r0, #0x4 /* data RAM */
38 orr r0, r0, #(1 << 24) /* disable write allocate delay */
39 orr r0, r0, #(1 << 23) /* disable write allocate combine */
40 orr r0, r0, #(1 << 22) /* disable write allocate */
42 #if defined(CONFIG_MX51)
44 ldr r3, [r1, #ROM_SI_REV]
47 /* disable write combine for TO 2 and lower revs */
48 orrls r0, r0, #(1 << 25)
51 mcr 15, 1, r0, c9, c0, 2
54 /* AIPS setup - Only setup MPROTx registers.
55 * The PACR default values are good.*/
58 * Set all MPROTx to be non-bufferable, trusted for R/W,
59 * not forced to user-mode.
61 ldr r0, =AIPS1_BASE_ADDR
65 ldr r0, =AIPS2_BASE_ADDR
69 * Clear the on and off peripheral modules Supervisor Protect bit
70 * for SDMA to access them. Did not change the AIPS control registers
71 * (offset 0x20) access type
78 /* VPU and IPU given higher priority (0x4)
79 * IPU accesses with ID=0x1 given highest priority (=0xA)
81 ldr r0, =M4IF_BASE_ADDR
98 .macro setup_pll pll, freq
101 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
103 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
105 ldr r1, W_DP_OP_\freq
106 str r1, [r0, #PLL_DP_OP]
107 str r1, [r0, #PLL_DP_HFS_OP]
109 ldr r1, W_DP_MFD_\freq
110 str r1, [r0, #PLL_DP_MFD]
111 str r1, [r0, #PLL_DP_HFS_MFD]
113 ldr r1, W_DP_MFN_\freq
114 str r1, [r0, #PLL_DP_MFN]
115 str r1, [r0, #PLL_DP_HFS_MFN]
118 str r1, [r0, #PLL_DP_CTL]
119 1: ldr r1, [r0, #PLL_DP_CTL]
125 ldr r0, =CCM_BASE_ADDR
127 #if defined(CONFIG_MX51)
128 /* Gate of clocks to the peripherals first */
130 str r1, [r0, #CLKCTL_CCGR0]
132 str r1, [r0, #CLKCTL_CCGR1]
133 str r1, [r0, #CLKCTL_CCGR2]
134 str r1, [r0, #CLKCTL_CCGR3]
137 str r1, [r0, #CLKCTL_CCGR4]
139 str r1, [r0, #CLKCTL_CCGR5]
141 str r1, [r0, #CLKCTL_CCGR6]
143 /* Disable IPU and HSC dividers */
145 str r1, [r0, #CLKCTL_CCDR]
147 /* Make sure to switch the DDR away from PLL 1 */
149 str r1, [r0, #CLKCTL_CBCDR]
150 /* make sure divider effective */
151 1: ldr r1, [r0, #CLKCTL_CDHIPR]
156 /* Switch ARM to step clock */
158 str r1, [r0, #CLKCTL_CCSR]
160 setup_pll PLL1_BASE_ADDR, 800
162 #if defined(CONFIG_MX51)
163 setup_pll PLL3_BASE_ADDR, 665
165 /* Switch peripheral to PLL 3 */
166 ldr r0, =CCM_BASE_ADDR
168 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
169 str r1, [r0, #CLKCTL_CBCMR]
171 str r1, [r0, #CLKCTL_CBCDR]
172 setup_pll PLL2_BASE_ADDR, 665
174 /* Switch peripheral to PLL2 */
175 ldr r0, =CCM_BASE_ADDR
177 str r1, [r0, #CLKCTL_CBCDR]
179 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
180 str r1, [r0, #CLKCTL_CBCMR]
182 setup_pll PLL3_BASE_ADDR, 216
184 /* Set the platform clock dividers */
185 ldr r0, =ARM_BASE_ADDR
189 ldr r0, =CCM_BASE_ADDR
191 #if defined(CONFIG_MX51)
192 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
194 ldr r3, [r1, #ROM_SI_REV]
202 str r1, [r0, #CLKCTL_CACRR]
203 /* Switch ARM back to PLL 1 */
205 str r1, [r0, #CLKCTL_CCSR]
207 #if defined(CONFIG_MX51)
209 /* Use lp_apm (24MHz) source for perclk */
211 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
212 str r1, [r0, #CLKCTL_CBCMR]
213 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
214 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
215 str r1, [r0, #CLKCTL_CBCDR]
218 /* Restore the default values in the Gate registers */
220 str r1, [r0, #CLKCTL_CCGR0]
221 str r1, [r0, #CLKCTL_CCGR1]
222 str r1, [r0, #CLKCTL_CCGR2]
223 str r1, [r0, #CLKCTL_CCGR3]
224 str r1, [r0, #CLKCTL_CCGR4]
225 str r1, [r0, #CLKCTL_CCGR5]
226 str r1, [r0, #CLKCTL_CCGR6]
227 #if defined(CONFIG_MX53)
228 str r1, [r0, #CLKCTL_CCGR7]
231 #if defined(CONFIG_MX51)
232 /* Use PLL 2 for UART's, get 66.5MHz from it */
234 str r1, [r0, #CLKCTL_CSCMR1]
236 str r1, [r0, #CLKCTL_CSCDR1]
237 #elif defined(CONFIG_MX53)
238 ldr r1, [r0, #CLKCTL_CSCDR1]
242 str r1, [r0, #CLKCTL_CSCDR1]
244 /* make sure divider effective */
245 1: ldr r1, [r0, #CLKCTL_CDHIPR]
250 str r1, [r0, #CLKCTL_CCDR]
252 /* for cko - for ARM div by 8 */
254 add r1, r1, #0x00000F0
255 str r1, [r0, #CLKCTL_CCOSR]
259 ldr r0, =WDOG1_BASE_ADDR
264 .section ".text.init", "x"
268 #if defined(CONFIG_MX51)
269 ldr r0, =GPIO1_BASE_ADDR
271 orr r1, r1, #(1 << 23)
274 orr r1, r1, #(1 << 23)
286 /* r12 saved upper lr*/
289 /* Board level setting value */
290 W_DP_OP_800: .word DP_OP_800
291 W_DP_MFD_800: .word DP_MFD_800
292 W_DP_MFN_800: .word DP_MFN_800
293 W_DP_OP_665: .word DP_OP_665
294 W_DP_MFD_665: .word DP_MFD_665
295 W_DP_MFN_665: .word DP_MFN_665
296 W_DP_OP_216: .word DP_OP_216
297 W_DP_MFD_216: .word DP_MFD_216
298 W_DP_MFN_216: .word DP_MFN_216