2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/asm-offsets.h>
27 * L2CC Cache setup/invalidation/disable
30 /* explicitly disable L2 cache */
31 mrc 15, 0, r0, c1, c0, 1
33 mcr 15, 0, r0, c1, c0, 1
35 /* reconfigure L2 cache aux control reg */
36 mov r0, #0xC0 /* tag RAM */
37 add r0, r0, #0x4 /* data RAM */
38 orr r0, r0, #(1 << 24) /* disable write allocate delay */
39 orr r0, r0, #(1 << 23) /* disable write allocate combine */
40 orr r0, r0, #(1 << 22) /* disable write allocate */
42 cmp r3, #0x10 /* r3 contains the silicon rev */
44 /* disable write combine for TO 2 and lower revs */
45 orrls r0, r0, #(1 << 25)
47 mcr 15, 1, r0, c9, c0, 2
50 /* AIPS setup - Only setup MPROTx registers.
51 * The PACR default values are good.*/
54 * Set all MPROTx to be non-bufferable, trusted for R/W,
55 * not forced to user-mode.
57 ldr r0, =AIPS1_BASE_ADDR
61 ldr r0, =AIPS2_BASE_ADDR
65 * Clear the on and off peripheral modules Supervisor Protect bit
66 * for SDMA to access them. Did not change the AIPS control registers
67 * (offset 0x20) access type
74 /* VPU and IPU given higher priority (0x4)
75 * IPU accesses with ID=0x1 given highest priority (=0xA)
77 ldr r0, =M4IF_BASE_ADDR
94 .macro setup_pll pll, freq
97 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
99 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
101 ldr r1, W_DP_OP_\freq
102 str r1, [r0, #PLL_DP_OP]
103 str r1, [r0, #PLL_DP_HFS_OP]
105 ldr r1, W_DP_MFD_\freq
106 str r1, [r0, #PLL_DP_MFD]
107 str r1, [r0, #PLL_DP_HFS_MFD]
109 ldr r1, W_DP_MFN_\freq
110 str r1, [r0, #PLL_DP_MFN]
111 str r1, [r0, #PLL_DP_HFS_MFN]
114 str r1, [r0, #PLL_DP_CTL]
115 1: ldr r1, [r0, #PLL_DP_CTL]
121 ldr r0, =CCM_BASE_ADDR
123 #if defined(CONFIG_MX51)
124 /* Gate of clocks to the peripherals first */
126 str r1, [r0, #CLKCTL_CCGR0]
128 str r1, [r0, #CLKCTL_CCGR1]
129 str r1, [r0, #CLKCTL_CCGR2]
130 str r1, [r0, #CLKCTL_CCGR3]
133 str r1, [r0, #CLKCTL_CCGR4]
135 str r1, [r0, #CLKCTL_CCGR5]
137 str r1, [r0, #CLKCTL_CCGR6]
139 /* Disable IPU and HSC dividers */
141 str r1, [r0, #CLKCTL_CCDR]
143 /* Make sure to switch the DDR away from PLL 1 */
145 str r1, [r0, #CLKCTL_CBCDR]
146 /* make sure divider effective */
147 1: ldr r1, [r0, #CLKCTL_CDHIPR]
152 /* Switch ARM to step clock */
154 str r1, [r0, #CLKCTL_CCSR]
156 setup_pll PLL1_BASE_ADDR, 800
158 #if defined(CONFIG_MX51)
159 setup_pll PLL3_BASE_ADDR, 665
161 /* Switch peripheral to PLL 3 */
162 ldr r0, =CCM_BASE_ADDR
164 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
165 str r1, [r0, #CLKCTL_CBCMR]
167 str r1, [r0, #CLKCTL_CBCDR]
168 setup_pll PLL2_BASE_ADDR, 665
170 /* Switch peripheral to PLL2 */
171 ldr r0, =CCM_BASE_ADDR
173 str r1, [r0, #CLKCTL_CBCDR]
175 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
176 str r1, [r0, #CLKCTL_CBCMR]
178 setup_pll PLL3_BASE_ADDR, 216
180 /* Set the platform clock dividers */
181 ldr r0, =ARM_BASE_ADDR
185 ldr r0, =CCM_BASE_ADDR
187 #if defined(CONFIG_MX51)
188 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
190 ldr r3, [r1, #ROM_SI_REV]
198 str r1, [r0, #CLKCTL_CACRR]
199 /* Switch ARM back to PLL 1 */
201 str r1, [r0, #CLKCTL_CCSR]
203 #if defined(CONFIG_MX51)
205 /* Use lp_apm (24MHz) source for perclk */
207 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
208 str r1, [r0, #CLKCTL_CBCMR]
209 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
210 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
211 str r1, [r0, #CLKCTL_CBCDR]
214 /* Restore the default values in the Gate registers */
216 str r1, [r0, #CLKCTL_CCGR0]
217 str r1, [r0, #CLKCTL_CCGR1]
218 str r1, [r0, #CLKCTL_CCGR2]
219 str r1, [r0, #CLKCTL_CCGR3]
220 str r1, [r0, #CLKCTL_CCGR4]
221 str r1, [r0, #CLKCTL_CCGR5]
222 str r1, [r0, #CLKCTL_CCGR6]
223 #if defined(CONFIG_MX53)
224 str r1, [r0, #CLKCTL_CCGR7]
227 #if defined(CONFIG_MX51)
228 /* Use PLL 2 for UART's, get 66.5MHz from it */
230 str r1, [r0, #CLKCTL_CSCMR1]
232 str r1, [r0, #CLKCTL_CSCDR1]
233 #elif defined(CONFIG_MX53)
234 ldr r1, [r0, #CLKCTL_CSCDR1]
238 str r1, [r0, #CLKCTL_CSCDR1]
240 /* make sure divider effective */
241 1: ldr r1, [r0, #CLKCTL_CDHIPR]
246 str r1, [r0, #CLKCTL_CCDR]
248 /* for cko - for ARM div by 8 */
250 add r1, r1, #0x00000F0
251 str r1, [r0, #CLKCTL_CCOSR]
255 ldr r0, =WDOG1_BASE_ADDR
260 .section ".text.init", "x"
264 #if defined(CONFIG_MX51)
265 ldr r0, =GPIO1_BASE_ADDR
267 orr r1, r1, #(1 << 23)
270 orr r1, r1, #(1 << 23)
282 /* r12 saved upper lr*/
285 /* Board level setting value */
286 W_DP_OP_800: .word DP_OP_800
287 W_DP_MFD_800: .word DP_MFD_800
288 W_DP_MFN_800: .word DP_MFN_800
289 W_DP_OP_665: .word DP_OP_665
290 W_DP_MFD_665: .word DP_MFD_665
291 W_DP_MFN_665: .word DP_MFN_665
292 W_DP_OP_216: .word DP_OP_216
293 W_DP_MFD_216: .word DP_MFD_216
294 W_DP_MFN_216: .word DP_MFN_216