2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/asm-offsets.h>
27 * L2CC Cache setup/invalidation/disable
30 /* explicitly disable L2 cache */
31 mrc 15, 0, r0, c1, c0, 1
33 mcr 15, 0, r0, c1, c0, 1
35 /* reconfigure L2 cache aux control reg */
36 mov r0, #0xC0 /* tag RAM */
37 add r0, r0, #0x4 /* data RAM */
38 orr r0, r0, #(1 << 24) /* disable write allocate delay */
39 orr r0, r0, #(1 << 23) /* disable write allocate combine */
40 orr r0, r0, #(1 << 22) /* disable write allocate */
42 cmp r3, #0x10 /* r3 contains the silicon rev */
44 /* disable write combine for TO 2 and lower revs */
45 orrls r0, r0, #(1 << 25)
47 mcr 15, 1, r0, c9, c0, 2
50 /* AIPS setup - Only setup MPROTx registers.
51 * The PACR default values are good.*/
54 * Set all MPROTx to be non-bufferable, trusted for R/W,
55 * not forced to user-mode.
57 ldr r0, =AIPS1_BASE_ADDR
61 ldr r0, =AIPS2_BASE_ADDR
65 * Clear the on and off peripheral modules Supervisor Protect bit
66 * for SDMA to access them. Did not change the AIPS control registers
67 * (offset 0x20) access type
73 /* VPU and IPU given higher priority (0x4)
74 * IPU accesses with ID=0x1 given highest priority (=0xA)
76 ldr r0, =M4IF_BASE_ADDR
92 .macro setup_pll pll, freq
95 str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
97 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
99 str r3, [r2, #PLL_DP_OP]
100 str r3, [r2, #PLL_DP_HFS_OP]
102 str r4, [r2, #PLL_DP_MFD]
103 str r4, [r2, #PLL_DP_HFS_MFD]
105 str r5, [r2, #PLL_DP_MFN]
106 str r5, [r2, #PLL_DP_HFS_MFN]
109 str r1, [r2, #PLL_DP_CTL]
110 1: ldr r1, [r2, #PLL_DP_CTL]
116 ldr r0, =CCM_BASE_ADDR
118 /* Gate of clocks to the peripherals first */
120 str r1, [r0, #CLKCTL_CCGR0]
122 str r1, [r0, #CLKCTL_CCGR1]
123 str r1, [r0, #CLKCTL_CCGR2]
124 str r1, [r0, #CLKCTL_CCGR3]
127 str r1, [r0, #CLKCTL_CCGR4]
129 str r1, [r0, #CLKCTL_CCGR5]
131 str r1, [r0, #CLKCTL_CCGR6]
133 /* Disable IPU and HSC dividers */
135 str r1, [r0, #CLKCTL_CCDR]
137 /* Make sure to switch the DDR away from PLL 1 */
139 str r1, [r0, #CLKCTL_CBCDR]
140 /* make sure divider effective */
141 1: ldr r1, [r0, #CLKCTL_CDHIPR]
145 /* Switch ARM to step clock */
147 str r1, [r0, #CLKCTL_CCSR]
151 setup_pll PLL1_BASE_ADDR
156 setup_pll PLL3_BASE_ADDR
158 /* Switch peripheral to PLL 3 */
159 ldr r0, =CCM_BASE_ADDR
161 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
162 str r1, [r0, #CLKCTL_CBCMR]
164 str r1, [r0, #CLKCTL_CBCDR]
168 setup_pll PLL2_BASE_ADDR
170 /* Switch peripheral to PLL2 */
171 ldr r0, =CCM_BASE_ADDR
173 str r1, [r0, #CLKCTL_CBCDR]
175 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
176 str r1, [r0, #CLKCTL_CBCMR]
181 setup_pll PLL3_BASE_ADDR
184 /* Set the platform clock dividers */
185 ldr r0, =ARM_BASE_ADDR
189 ldr r0, =CCM_BASE_ADDR
191 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
193 ldr r3, [r1, #ROM_SI_REV]
197 str r1, [r0, #CLKCTL_CACRR]
199 /* Switch ARM back to PLL 1 */
201 str r1, [r0, #CLKCTL_CCSR]
204 /* Use lp_apm (24MHz) source for perclk */
206 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
207 str r1, [r0, #CLKCTL_CBCMR]
208 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
209 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
210 str r1, [r0, #CLKCTL_CBCDR]
212 /* Restore the default values in the Gate registers */
214 str r1, [r0, #CLKCTL_CCGR0]
215 str r1, [r0, #CLKCTL_CCGR1]
216 str r1, [r0, #CLKCTL_CCGR2]
217 str r1, [r0, #CLKCTL_CCGR3]
218 str r1, [r0, #CLKCTL_CCGR4]
219 str r1, [r0, #CLKCTL_CCGR5]
220 str r1, [r0, #CLKCTL_CCGR6]
222 /* Use PLL 2 for UART's, get 66.5MHz from it */
224 str r1, [r0, #CLKCTL_CSCMR1]
226 str r1, [r0, #CLKCTL_CSCDR1]
228 /* make sure divider effective */
229 1: ldr r1, [r0, #CLKCTL_CDHIPR]
234 str r1, [r0, #CLKCTL_CCDR]
236 /* for cko - for ARM div by 8 */
238 add r1, r1, #0x00000F0
239 str r1, [r0, #CLKCTL_CCOSR]
243 ldr r0, =WDOG1_BASE_ADDR
248 .section ".text.init", "x"
252 ldr r0, =GPIO1_BASE_ADDR
254 orr r1, r1, #(1 << 23)
257 orr r1, r1, #(1 << 23)
268 /* r12 saved upper lr*/
271 /* Board level setting value */
272 DDR_PERCHARGE_CMD: .word 0x04008008
273 DDR_REFRESH_CMD: .word 0x00008010
274 DDR_LMR1_W: .word 0x00338018
275 DDR_LMR_CMD: .word 0xB2220000
276 DDR_TIMING_W: .word 0xB02567A9
277 DDR_MISC_W: .word 0x000A0104