2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
27 * L2CC Cache setup/invalidation/disable
30 /* explicitly disable L2 cache */
31 mrc 15, 0, r0, c1, c0, 1
33 mcr 15, 0, r0, c1, c0, 1
35 /* reconfigure L2 cache aux control reg */
36 mov r0, #0xC0 /* tag RAM */
37 add r0, r0, #0x4 /* data RAM */
38 orr r0, r0, #(1 << 24) /* disable write allocate delay */
39 orr r0, r0, #(1 << 23) /* disable write allocate combine */
40 orr r0, r0, #(1 << 22) /* disable write allocate */
42 #if defined(CONFIG_MX51)
44 ldr r3, [r1, #ROM_SI_REV]
47 /* disable write combine for TO 2 and lower revs */
48 orrls r0, r0, #(1 << 25)
51 mcr 15, 1, r0, c9, c0, 2
54 /* AIPS setup - Only setup MPROTx registers.
55 * The PACR default values are good.*/
58 * Set all MPROTx to be non-bufferable, trusted for R/W,
59 * not forced to user-mode.
61 ldr r0, =AIPS1_BASE_ADDR
65 ldr r0, =AIPS2_BASE_ADDR
69 * Clear the on and off peripheral modules Supervisor Protect bit
70 * for SDMA to access them. Did not change the AIPS control registers
71 * (offset 0x20) access type
78 /* VPU and IPU given higher priority (0x4)
79 * IPU accesses with ID=0x1 given highest priority (=0xA)
81 ldr r0, =M4IF_BASE_ADDR
98 .macro setup_pll pll, freq
101 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
103 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
105 ldr r1, W_DP_OP_\freq
106 str r1, [r0, #PLL_DP_OP]
107 str r1, [r0, #PLL_DP_HFS_OP]
109 ldr r1, W_DP_MFD_\freq
110 str r1, [r0, #PLL_DP_MFD]
111 str r1, [r0, #PLL_DP_HFS_MFD]
113 ldr r1, W_DP_MFN_\freq
114 str r1, [r0, #PLL_DP_MFN]
115 str r1, [r0, #PLL_DP_HFS_MFN]
118 str r1, [r0, #PLL_DP_CTL]
119 1: ldr r1, [r0, #PLL_DP_CTL]
124 .macro setup_pll_errata pll, freq
127 str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
129 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
130 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
135 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
136 str r5, [r2, #PLL_DP_HFS_MFN]
139 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
141 2: ldr r1, [r2, #PLL_DP_CONFIG]
145 ldr r1, =100 /* Wait at least 4 us */
150 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
154 ldr r0, =CCM_BASE_ADDR
156 #if defined(CONFIG_MX51)
157 /* Gate of clocks to the peripherals first */
159 str r1, [r0, #CLKCTL_CCGR0]
161 str r1, [r0, #CLKCTL_CCGR1]
162 str r1, [r0, #CLKCTL_CCGR2]
163 str r1, [r0, #CLKCTL_CCGR3]
166 str r1, [r0, #CLKCTL_CCGR4]
168 str r1, [r0, #CLKCTL_CCGR5]
170 str r1, [r0, #CLKCTL_CCGR6]
172 /* Disable IPU and HSC dividers */
174 str r1, [r0, #CLKCTL_CCDR]
176 /* Make sure to switch the DDR away from PLL 1 */
178 str r1, [r0, #CLKCTL_CBCDR]
179 /* make sure divider effective */
180 1: ldr r1, [r0, #CLKCTL_CDHIPR]
185 str r1, [r0, #CLKCTL_CCGR0]
187 str r1, [r0, #CLKCTL_CCGR1]
188 str r1, [r0, #CLKCTL_CCGR2]
189 str r1, [r0, #CLKCTL_CCGR3]
190 str r1, [r0, #CLKCTL_CCGR7]
193 str r1, [r0, #CLKCTL_CCGR4]
195 str r1, [r0, #CLKCTL_CCGR5]
197 str r1, [r0, #CLKCTL_CCGR6]
200 /* Switch ARM to step clock */
202 str r1, [r0, #CLKCTL_CCSR]
204 #if defined(CONFIG_MX51_PLL_ERRATA)
205 setup_pll PLL1_BASE_ADDR, 864
206 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
208 setup_pll PLL1_BASE_ADDR, 800
211 #if defined(CONFIG_MX51)
212 setup_pll PLL3_BASE_ADDR, 665
214 /* Switch peripheral to PLL 3 */
215 ldr r0, =CCM_BASE_ADDR
217 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
218 str r1, [r0, #CLKCTL_CBCMR]
220 str r1, [r0, #CLKCTL_CBCDR]
221 setup_pll PLL2_BASE_ADDR, 665
223 /* Switch peripheral to PLL2 */
224 ldr r0, =CCM_BASE_ADDR
226 str r1, [r0, #CLKCTL_CBCDR]
228 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
229 str r1, [r0, #CLKCTL_CBCMR]
231 setup_pll PLL3_BASE_ADDR, 216
233 /* Set the platform clock dividers */
234 ldr r0, =ARM_BASE_ADDR
238 ldr r0, =CCM_BASE_ADDR
240 #if defined(CONFIG_MX51)
241 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
243 ldr r3, [r1, #ROM_SI_REV]
251 str r1, [r0, #CLKCTL_CACRR]
252 /* Switch ARM back to PLL 1 */
254 str r1, [r0, #CLKCTL_CCSR]
256 #if defined(CONFIG_MX51)
258 /* Use lp_apm (24MHz) source for perclk */
260 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
261 str r1, [r0, #CLKCTL_CBCMR]
262 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
263 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
264 str r1, [r0, #CLKCTL_CBCDR]
267 /* Restore the default values in the Gate registers */
269 str r1, [r0, #CLKCTL_CCGR0]
270 str r1, [r0, #CLKCTL_CCGR1]
271 str r1, [r0, #CLKCTL_CCGR2]
272 str r1, [r0, #CLKCTL_CCGR3]
273 str r1, [r0, #CLKCTL_CCGR4]
274 str r1, [r0, #CLKCTL_CCGR5]
275 str r1, [r0, #CLKCTL_CCGR6]
276 #if defined(CONFIG_MX53)
277 str r1, [r0, #CLKCTL_CCGR7]
280 #if defined(CONFIG_MX51)
281 /* Use PLL 2 for UART's, get 66.5MHz from it */
283 str r1, [r0, #CLKCTL_CSCMR1]
285 str r1, [r0, #CLKCTL_CSCDR1]
286 #elif defined(CONFIG_MX53)
287 /* Switch peripheral to PLL2 */
288 ldr r0, =CCM_BASE_ADDR
290 orr r1, r1, #(2 << 10)
291 orr r1, r1, #(0 << 16)
292 orr r1, r1, #(1 << 19)
293 str r1, [r0, #CLKCTL_CBCDR]
296 str r1, [r0, #CLKCTL_CBCMR]
297 /* Change uart clk parent to pll2*/
298 ldr r1, [r0, #CLKCTL_CSCMR1]
299 and r1, r1, #0xfcffffff
300 orr r1, r1, #0x01000000
301 str r1, [r0, #CLKCTL_CSCMR1]
302 ldr r1, [r0, #CLKCTL_CSCDR1]
303 and r1, r1, #0xffffffc0
305 str r1, [r0, #CLKCTL_CSCDR1]
307 /* make sure divider effective */
308 1: ldr r1, [r0, #CLKCTL_CDHIPR]
313 str r1, [r0, #CLKCTL_CCDR]
315 /* for cko - for ARM div by 8 */
317 add r1, r1, #0x00000F0
318 str r1, [r0, #CLKCTL_CCOSR]
322 ldr r0, =WDOG1_BASE_ADDR
327 .section ".text.init", "x"
331 #if defined(CONFIG_MX51)
332 ldr r0, =GPIO1_BASE_ADDR
334 orr r1, r1, #(1 << 23)
337 orr r1, r1, #(1 << 23)
349 /* r12 saved upper lr*/
352 /* Board level setting value */
353 W_DP_OP_864: .word DP_OP_864
354 W_DP_MFD_864: .word DP_MFD_864
355 W_DP_MFN_864: .word DP_MFN_864
356 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
357 W_DP_OP_800: .word DP_OP_800
358 W_DP_MFD_800: .word DP_MFD_800
359 W_DP_MFN_800: .word DP_MFN_800
360 W_DP_OP_665: .word DP_OP_665
361 W_DP_MFD_665: .word DP_MFD_665
362 W_DP_MFN_665: .word DP_MFN_665
363 W_DP_OP_216: .word DP_OP_216
364 W_DP_MFD_216: .word DP_MFD_216
365 W_DP_MFN_216: .word DP_MFN_216