2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <generated/asm-offsets.h>
12 #include <linux/linkage.h>
14 .section ".text.init", "x"
16 .macro init_arm_erratum
17 /* ARM erratum ID #468414 */
18 mrc 15, 0, r1, c1, c0, 1
19 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
20 mcr 15, 0, r1, c1, c0, 1
24 * L2CC Cache setup/invalidation/disable
27 /* explicitly disable L2 cache */
28 mrc 15, 0, r0, c1, c0, 1
30 mcr 15, 0, r0, c1, c0, 1
32 /* reconfigure L2 cache aux control reg */
33 ldr r0, =0xC0 | /* tag RAM */ \
34 0x4 | /* data RAM */ \
35 1 << 24 | /* disable write allocate delay */ \
36 1 << 23 | /* disable write allocate combine */ \
37 1 << 22 /* disable write allocate */
39 #if defined(CONFIG_MX51)
40 ldr r3, [r4, #ROM_SI_REV]
43 /* disable write combine for TO 2 and lower revs */
44 orrls r0, r0, #1 << 25
47 mcr 15, 1, r0, c9, c0, 2
50 /* AIPS setup - Only setup MPROTx registers.
51 * The PACR default values are good.*/
54 * Set all MPROTx to be non-bufferable, trusted for R/W,
55 * not forced to user-mode.
57 ldr r0, =AIPS1_BASE_ADDR
61 ldr r0, =AIPS2_BASE_ADDR
65 * Clear the on and off peripheral modules Supervisor Protect bit
66 * for SDMA to access them. Did not change the AIPS control registers
67 * (offset 0x20) access type
74 /* VPU and IPU given higher priority (0x4)
75 * IPU accesses with ID=0x1 given highest priority (=0xA)
77 ldr r0, =M4IF_BASE_ADDR
93 .macro setup_pll pll, freq
105 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
107 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
109 ldr r1, [r2, #W_DP_OP]
110 str r1, [r0, #PLL_DP_OP]
111 str r1, [r0, #PLL_DP_HFS_OP]
113 ldr r1, [r2, #W_DP_MFD]
114 str r1, [r0, #PLL_DP_MFD]
115 str r1, [r0, #PLL_DP_HFS_MFD]
117 ldr r1, [r2, #W_DP_MFN]
118 str r1, [r0, #PLL_DP_MFN]
119 str r1, [r0, #PLL_DP_HFS_MFN]
122 str r1, [r0, #PLL_DP_CTL]
123 1: ldr r1, [r0, #PLL_DP_CTL]
127 /* r10 saved upper lr */
130 .macro setup_pll_errata pll, freq
132 str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
134 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
135 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
140 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
141 str r5, [r2, #PLL_DP_HFS_MFN]
144 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
146 2: ldr r1, [r2, #PLL_DP_CONFIG]
150 ldr r1, =100 /* Wait at least 4 us */
155 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
159 #if defined (CONFIG_MX51)
160 ldr r0, =CCM_BASE_ADDR
162 /* Gate of clocks to the peripherals first */
164 str r1, [r0, #CLKCTL_CCGR0]
165 str r4, [r0, #CLKCTL_CCGR1]
166 str r4, [r0, #CLKCTL_CCGR2]
167 str r4, [r0, #CLKCTL_CCGR3]
170 str r1, [r0, #CLKCTL_CCGR4]
172 str r1, [r0, #CLKCTL_CCGR5]
174 str r1, [r0, #CLKCTL_CCGR6]
176 /* Disable IPU and HSC dividers */
178 str r1, [r0, #CLKCTL_CCDR]
180 /* Make sure to switch the DDR away from PLL 1 */
182 str r1, [r0, #CLKCTL_CBCDR]
183 /* make sure divider effective */
184 1: ldr r1, [r0, #CLKCTL_CDHIPR]
188 /* Switch ARM to step clock */
190 str r1, [r0, #CLKCTL_CCSR]
192 #if defined(CONFIG_MX51_PLL_ERRATA)
193 setup_pll PLL1_BASE_ADDR, 864
194 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
196 setup_pll PLL1_BASE_ADDR, 800
199 setup_pll PLL3_BASE_ADDR, 665
201 /* Switch peripheral to PLL 3 */
202 ldr r0, =CCM_BASE_ADDR
203 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
204 str r1, [r0, #CLKCTL_CBCMR]
206 str r1, [r0, #CLKCTL_CBCDR]
207 setup_pll PLL2_BASE_ADDR, 665
209 /* Switch peripheral to PLL2 */
210 ldr r0, =CCM_BASE_ADDR
212 str r1, [r0, #CLKCTL_CBCDR]
213 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
214 str r1, [r0, #CLKCTL_CBCMR]
216 setup_pll PLL3_BASE_ADDR, 216
218 /* Set the platform clock dividers */
219 ldr r0, =ARM_BASE_ADDR
223 ldr r0, =CCM_BASE_ADDR
225 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
226 ldr r3, [r4, #ROM_SI_REV]
231 str r1, [r0, #CLKCTL_CACRR]
233 /* Switch ARM back to PLL 1 */
234 str r4, [r0, #CLKCTL_CCSR]
237 /* Use lp_apm (24MHz) source for perclk */
238 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
239 str r1, [r0, #CLKCTL_CBCMR]
240 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
241 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
242 str r1, [r0, #CLKCTL_CBCDR]
244 /* Restore the default values in the Gate registers */
246 str r1, [r0, #CLKCTL_CCGR0]
247 str r1, [r0, #CLKCTL_CCGR1]
248 str r1, [r0, #CLKCTL_CCGR2]
249 str r1, [r0, #CLKCTL_CCGR3]
250 str r1, [r0, #CLKCTL_CCGR4]
251 str r1, [r0, #CLKCTL_CCGR5]
252 str r1, [r0, #CLKCTL_CCGR6]
254 /* Use PLL 2 for UART's, get 66.5MHz from it */
256 str r1, [r0, #CLKCTL_CSCMR1]
258 str r1, [r0, #CLKCTL_CSCDR1]
259 /* make sure divider effective */
260 1: ldr r1, [r0, #CLKCTL_CDHIPR]
264 str r4, [r0, #CLKCTL_CCDR]
266 /* for cko - for ARM div by 8 */
268 add r1, r1, #0x00000F0
269 str r1, [r0, #CLKCTL_CCOSR]
270 #else /* CONFIG_MX53 */
271 ldr r0, =CCM_BASE_ADDR
273 /* Gate of clocks to the peripherals first */
275 str r1, [r0, #CLKCTL_CCGR0]
276 str r4, [r0, #CLKCTL_CCGR1]
277 str r4, [r0, #CLKCTL_CCGR2]
278 str r4, [r0, #CLKCTL_CCGR3]
279 str r4, [r0, #CLKCTL_CCGR7]
281 str r1, [r0, #CLKCTL_CCGR4]
283 str r1, [r0, #CLKCTL_CCGR5]
285 str r1, [r0, #CLKCTL_CCGR6]
287 /* Switch ARM to step clock */
289 str r1, [r0, #CLKCTL_CCSR]
291 setup_pll PLL1_BASE_ADDR, 800
293 setup_pll PLL3_BASE_ADDR, 400
295 /* Switch peripheral to PLL3 */
296 ldr r0, =CCM_BASE_ADDR
298 str r1, [r0, #CLKCTL_CBCMR]
300 str r1, [r0, #CLKCTL_CBCDR]
301 /* make sure change is effective */
302 1: ldr r1, [r0, #CLKCTL_CDHIPR]
306 setup_pll PLL2_BASE_ADDR, 400
308 /* Switch peripheral to PLL2 */
309 ldr r0, =CCM_BASE_ADDR
311 str r1, [r0, #CLKCTL_CBCDR]
314 str r1, [r0, #CLKCTL_CBCMR]
316 /*change uart clk parent to pll2*/
317 ldr r1, [r0, #CLKCTL_CSCMR1]
318 and r1, r1, #0xfcffffff
319 orr r1, r1, #0x01000000
320 str r1, [r0, #CLKCTL_CSCMR1]
322 /* make sure change is effective */
323 1: ldr r1, [r0, #CLKCTL_CDHIPR]
327 setup_pll PLL3_BASE_ADDR, 216
329 setup_pll PLL4_BASE_ADDR, 455
331 /* Set the platform clock dividers */
332 ldr r0, =ARM_BASE_ADDR
336 ldr r0, =CCM_BASE_ADDR
338 str r1, [r0, #CLKCTL_CACRR]
340 /* Switch ARM back to PLL 1. */
342 str r1, [r0, #CLKCTL_CCSR]
344 /* make uart div=6 */
345 ldr r1, [r0, #CLKCTL_CSCDR1]
346 and r1, r1, #0xffffffc0
348 str r1, [r0, #CLKCTL_CSCDR1]
350 /* Restore the default values in the Gate registers */
352 str r1, [r0, #CLKCTL_CCGR0]
353 str r1, [r0, #CLKCTL_CCGR1]
354 str r1, [r0, #CLKCTL_CCGR2]
355 str r1, [r0, #CLKCTL_CCGR3]
356 str r1, [r0, #CLKCTL_CCGR4]
357 str r1, [r0, #CLKCTL_CCGR5]
358 str r1, [r0, #CLKCTL_CCGR6]
359 str r1, [r0, #CLKCTL_CCGR7]
362 str r1, [r0, #CLKCTL_CCDR]
364 /* for cko - for ARM div by 8 */
366 add r1, r1, #0x00000F0
367 str r1, [r0, #CLKCTL_CCOSR]
369 #endif /* CONFIG_MX53 */
373 ldr r0, =WDOG1_BASE_ADDR
380 mov r4, #0 /* Fix R4 to 0 */
382 #if defined(CONFIG_SYS_MAIN_PWR_ON)
383 ldr r0, =GPIO1_BASE_ADDR
403 ENDPROC(lowlevel_init)
405 /* Board level setting value */
406 #if defined(CONFIG_MX51_PLL_ERRATA)
407 W_DP_864: .word DP_OP_864
410 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
412 W_DP_800: .word DP_OP_800
416 #if defined(CONFIG_MX51)
417 W_DP_665: .word DP_OP_665
421 W_DP_216: .word DP_OP_216
424 W_DP_400: .word DP_OP_400
427 W_DP_455: .word DP_OP_455