3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
45 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
46 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
47 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
48 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
50 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
54 #define AHB_CLK_ROOT 133333333
55 #define SZ_DEC_1M 1000000
56 #define PLL_PD_MAX 16 /* Actual pd+1 */
57 #define PLL_MFI_MAX 15
65 #define MX5_CBCMR 0x00015154
66 #define MX5_CBCDR 0x02888945
68 struct fixed_pll_mfd {
73 const struct fixed_pll_mfd fixed_mfd[] = {
84 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
85 #define PLL_FREQ_MIN(ref_clk) \
86 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
87 #define MAX_DDR_CLK 420000000
88 #define NFC_CLK_MAX 34000000
90 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
92 void set_usboh3_clk(void)
94 clrsetbits_le32(&mxc_ccm->cscmr1,
95 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
96 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
97 clrsetbits_le32(&mxc_ccm->cscdr1,
98 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
99 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
100 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
101 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
104 void enable_usboh3_clk(unsigned char enable)
106 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
108 clrsetbits_le32(&mxc_ccm->CCGR2,
109 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
110 MXC_CCM_CCGR2_USBOH3_60M(cg));
113 #ifdef CONFIG_I2C_MXC
114 /* i2c_num can be from 0 - 2 */
115 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
121 mask = MXC_CCM_CCGR_CG_MASK <<
122 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
124 setbits_le32(&mxc_ccm->CCGR1, mask);
126 clrbits_le32(&mxc_ccm->CCGR1, mask);
131 void set_usb_phy_clk(void)
133 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
136 #if defined(CONFIG_MX51)
137 void enable_usb_phy1_clk(unsigned char enable)
139 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
141 clrsetbits_le32(&mxc_ccm->CCGR2,
142 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
143 MXC_CCM_CCGR2_USB_PHY(cg));
146 void enable_usb_phy2_clk(unsigned char enable)
148 /* i.MX51 has a single USB PHY clock, so do nothing here. */
150 #elif defined(CONFIG_MX53)
151 void enable_usb_phy1_clk(unsigned char enable)
153 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
155 clrsetbits_le32(&mxc_ccm->CCGR4,
156 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
157 MXC_CCM_CCGR4_USB_PHY1(cg));
160 void enable_usb_phy2_clk(unsigned char enable)
162 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
164 clrsetbits_le32(&mxc_ccm->CCGR4,
165 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
166 MXC_CCM_CCGR4_USB_PHY2(cg));
171 * Calculate the frequency of PLLn.
173 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
175 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
176 uint64_t refclk, temp;
179 ctrl = readl(&pll->ctrl);
181 if (ctrl & MXC_DPLLC_CTL_HFSM) {
182 mfn = readl(&pll->hfs_mfn);
183 mfd = readl(&pll->hfs_mfd);
184 op = readl(&pll->hfs_op);
186 mfn = readl(&pll->mfn);
187 mfd = readl(&pll->mfd);
188 op = readl(&pll->op);
191 mfd &= MXC_DPLLC_MFD_MFD_MASK;
192 mfn &= MXC_DPLLC_MFN_MFN_MASK;
193 pdf = op & MXC_DPLLC_OP_PDF_MASK;
194 mfi = MXC_DPLLC_OP_MFI_RD(op);
201 if (mfn >= 0x04000000) {
208 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
211 do_div(refclk, pdf + 1);
212 temp = refclk * mfn_abs;
213 do_div(temp, mfd + 1);
227 u32 get_mcu_main_clk(void)
231 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
232 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
233 return freq / (reg + 1);
237 * Get the rate of peripheral's root clock.
239 u32 get_periph_clk(void)
243 reg = readl(&mxc_ccm->cbcdr);
244 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
245 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
246 reg = readl(&mxc_ccm->cbcmr);
247 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
249 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
251 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
259 * Get the rate of ipg clock.
261 static u32 get_ipg_clk(void)
263 uint32_t freq, reg, div;
265 freq = get_ahb_clk();
267 reg = readl(&mxc_ccm->cbcdr);
268 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
274 * Get the rate of ipg_per clock.
276 static u32 get_ipg_per_clk(void)
278 u32 pred1, pred2, podf;
280 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
281 return get_ipg_clk();
282 /* Fixme: not handle what about lpm*/
283 podf = readl(&mxc_ccm->cbcdr);
284 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
285 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
286 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
287 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
291 * Get the rate of uart clk.
293 static u32 get_uart_clk(void)
295 unsigned int freq, reg, pred, podf;
297 reg = readl(&mxc_ccm->cscmr1);
298 switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
300 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
303 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
306 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
312 reg = readl(&mxc_ccm->cscdr1);
313 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
314 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
315 freq /= (pred + 1) * (podf + 1);
321 * This function returns the low power audio clock.
323 static u32 get_lp_apm(void)
326 u32 ccsr = readl(&mxc_ccm->ccsr);
328 if (ccsr & MXC_CCM_CCSR_LP_APM)
329 ret_val = MXC_CLK32 * 1024;
337 * get cspi clock rate.
339 static u32 imx_get_cspiclk(void)
341 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
342 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
343 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
345 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
346 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
347 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
351 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK) /
352 ((pre_pdf + 1) * (pdf + 1));
355 ret_val = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK) /
356 ((pre_pdf + 1) * (pdf + 1));
359 ret_val = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK) /
360 ((pre_pdf + 1) * (pdf + 1));
363 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
370 static u32 get_axi_a_clk(void)
372 u32 cbcdr = readl(&mxc_ccm->cbcdr);
373 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
375 return get_periph_clk() / (pdf + 1);
378 static u32 get_axi_b_clk(void)
380 u32 cbcdr = readl(&mxc_ccm->cbcdr);
381 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
383 return get_periph_clk() / (pdf + 1);
386 static u32 get_emi_slow_clk(void)
388 u32 cbcdr = readl(&mxc_ccm->cbcdr);
389 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
390 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
393 return get_ahb_clk() / (pdf + 1);
395 return get_periph_clk() / (pdf + 1);
398 static u32 get_ddr_clk(void)
401 u32 cbcmr = readl(&mxc_ccm->cbcmr);
402 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
404 u32 cbcdr = readl(&mxc_ccm->cbcdr);
405 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
406 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
408 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
409 ret_val /= ddr_clk_podf + 1;
414 switch (ddr_clk_sel) {
416 ret_val = get_axi_a_clk();
419 ret_val = get_axi_b_clk();
422 ret_val = get_emi_slow_clk();
425 ret_val = get_ahb_clk();
435 * The API of get mxc clocks.
437 unsigned int mxc_get_clock(enum mxc_clock clk)
441 return get_mcu_main_clk();
443 return get_ahb_clk();
445 return get_ipg_clk();
448 return get_ipg_per_clk();
450 return get_uart_clk();
452 return imx_get_cspiclk();
454 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
456 return get_ahb_clk();
458 return get_ddr_clk();
465 u32 imx_get_uartclk(void)
467 return get_uart_clk();
471 u32 imx_get_fecclk(void)
473 return mxc_get_clock(MXC_IPG_CLK);
476 static int gcd(int m, int n)
491 * This is to calculate various parameters based on reference clock and
492 * targeted clock based on the equation:
493 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
494 * This calculation is based on a fixed MFD value for simplicity.
496 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
498 u64 pd, mfi = 1, mfn, mfd, t1;
499 u32 n_target = target;
503 * Make sure targeted freq is in the valid range.
504 * Otherwise the following calculation might be wrong!!!
506 if (n_target < PLL_FREQ_MIN(ref) ||
507 n_target > PLL_FREQ_MAX(ref)) {
508 printf("Targeted peripheral clock should be"
509 "within [%d - %d]\n",
510 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
511 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
515 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
516 if (fixed_mfd[i].ref_clk_hz == ref) {
517 mfd = fixed_mfd[i].mfd;
522 if (i == ARRAY_SIZE(fixed_mfd))
525 /* Use n_target and n_ref to avoid overflow */
526 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
528 do_div(t1, (4 * n_ref));
530 if (mfi > PLL_MFI_MAX)
537 * Now got pd and mfi already
539 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
547 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
548 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
562 #define calc_div(tgt_clk, src_clk, limit) ({ \
564 if (((src_clk) % (tgt_clk)) <= 100) \
565 v = (src_clk) / (tgt_clk); \
567 v = ((src_clk) / (tgt_clk)) + 1;\
573 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
575 writel(0x1232, &pll->ctrl); \
576 writel(0x2, &pll->config); \
577 writel((((pd) - 1) << 0) | ((fi) << 4), \
579 writel(fn, &(pll->mfn)); \
580 writel((fd) - 1, &pll->mfd); \
581 writel((((pd) - 1) << 0) | ((fi) << 4), \
583 writel(fn, &pll->hfs_mfn); \
584 writel((fd) - 1, &pll->hfs_mfd); \
585 writel(0x1232, &pll->ctrl); \
586 while (!readl(&pll->ctrl) & 0x1) \
590 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
592 u32 ccsr = readl(&mxc_ccm->ccsr);
593 struct mxc_pll_reg *pll = mxc_plls[index];
597 /* Switch ARM to PLL2 clock */
598 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
600 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
601 pll_param->mfi, pll_param->mfn,
604 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
608 /* Switch to pll2 bypass clock */
609 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
611 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
612 pll_param->mfi, pll_param->mfn,
615 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
619 /* Switch to pll3 bypass clock */
620 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
622 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
623 pll_param->mfi, pll_param->mfn,
626 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
631 /* Switch to pll4 bypass clock */
632 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
634 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
635 pll_param->mfi, pll_param->mfn,
638 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
649 /* Config CPU clock */
650 static int config_core_clk(u32 ref, u32 freq)
653 struct pll_param pll_param;
655 memset(&pll_param, 0, sizeof(struct pll_param));
657 /* The case that periph uses PLL1 is not considered here */
658 ret = calc_pll_params(ref, freq, &pll_param);
660 printf("Error:Can't find pll parameters: %d\n", ret);
664 return config_pll_clk(PLL1_CLOCK, &pll_param);
667 static int config_nfc_clk(u32 nfc_clk)
669 u32 parent_rate = get_emi_slow_clk();
670 u32 div = parent_rate / nfc_clk;
676 if (parent_rate / div > NFC_CLK_MAX)
678 clrsetbits_le32(&mxc_ccm->cbcdr,
679 MXC_CCM_CBCDR_NFC_PODF_MASK,
680 MXC_CCM_CBCDR_NFC_PODF(div - 1));
681 while (readl(&mxc_ccm->cdhipr) != 0)
686 /* Config main_bus_clock for periphs */
687 static int config_periph_clk(u32 ref, u32 freq)
690 struct pll_param pll_param;
692 memset(&pll_param, 0, sizeof(struct pll_param));
694 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
695 ret = calc_pll_params(ref, freq, &pll_param);
697 printf("Error:Can't find pll parameters: %d\n",
701 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
702 readl(&mxc_ccm->cbcmr))) {
704 return config_pll_clk(PLL1_CLOCK, &pll_param);
707 return config_pll_clk(PLL3_CLOCK, &pll_param);
717 static int config_ddr_clk(u32 emi_clk)
720 s32 shift = 0, clk_sel, div = 1;
721 u32 cbcmr = readl(&mxc_ccm->cbcmr);
723 if (emi_clk > MAX_DDR_CLK) {
724 printf("Warning:DDR clock should not exceed %d MHz\n",
725 MAX_DDR_CLK / SZ_DEC_1M);
726 emi_clk = MAX_DDR_CLK;
729 clk_src = get_periph_clk();
730 /* Find DDR clock input */
731 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
749 if ((clk_src % emi_clk) < 10000000)
750 div = clk_src / emi_clk;
752 div = (clk_src / emi_clk) + 1;
756 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
757 while (readl(&mxc_ccm->cdhipr) != 0)
759 writel(0x0, &mxc_ccm->ccdr);
765 * This function assumes the expected core clock has to be changed by
766 * modifying the PLL. This is NOT true always but for most of the times,
767 * it is. So it assumes the PLL output freq is the same as the expected
768 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
769 * In the latter case, it will try to increase the presc value until
770 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
771 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
772 * on the targeted PLL and reference input clock to the PLL. Lastly,
773 * it sets the register based on these values along with the dividers.
774 * Note 1) There is no value checking for the passed-in divider values
775 * so the caller has to make sure those values are sensible.
776 * 2) Also adjust the NFC divider such that the NFC clock doesn't
777 * exceed NFC_CLK_MAX.
778 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
779 * 177MHz for higher voltage, this function fixes the max to 133MHz.
780 * 4) This function should not have allowed diag_printf() calls since
781 * the serial driver has been stoped. But leave then here to allow
782 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
784 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
790 if (config_core_clk(ref, freq))
794 if (config_periph_clk(ref, freq))
798 if (config_ddr_clk(freq))
802 if (config_nfc_clk(freq))
806 printf("Warning:Unsupported or invalid clock type\n");
814 * The clock for the external interface can be set to use internal clock
815 * if fuse bank 4, row 3, bit 2 is set.
816 * This is an undocumented feature and it was confirmed by Freescale's support:
817 * Fuses (but not pins) may be used to configure SATA clocks.
818 * Particularly the i.MX53 Fuse_Map contains the next information
819 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
820 * '00' - 100MHz (External)
821 * '01' - 50MHz (External)
822 * '10' - 120MHz, internal (USB PHY)
825 void mxc_set_sata_internal_clock(void)
828 (u32 *)(IIM_BASE_ADDR + 0x180c);
832 clrsetbits_le32(tmp_base, 0x6, 0x4);
837 * Dump some core clockes.
839 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
843 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
844 printf("PLL1 %8d MHz\n", freq / 1000000);
845 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
846 printf("PLL2 %8d MHz\n", freq / 1000000);
847 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
848 printf("PLL3 %8d MHz\n", freq / 1000000);
850 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
851 printf("PLL4 %8d MHz\n", freq / 1000000);
855 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
856 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
857 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
858 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
863 /***************************************************/
866 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,