3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
43 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
44 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
45 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
46 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
48 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
52 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
54 void set_usboh3_clk(void)
58 reg = readl(&mxc_ccm->cscmr1) &
59 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
60 reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
61 writel(reg, &mxc_ccm->cscmr1);
63 reg = readl(&mxc_ccm->cscdr1);
64 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
65 reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
66 reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
67 reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
69 writel(reg, &mxc_ccm->cscdr1);
72 void enable_usboh3_clk(unsigned char enable)
76 reg = readl(&mxc_ccm->CCGR2);
78 reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
80 reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
81 writel(reg, &mxc_ccm->CCGR2);
84 void set_usb_phy1_clk(void)
88 reg = readl(&mxc_ccm->cscmr1);
89 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
90 writel(reg, &mxc_ccm->cscmr1);
93 void enable_usb_phy1_clk(unsigned char enable)
97 reg = readl(&mxc_ccm->CCGR4);
99 reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
101 reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
102 writel(reg, &mxc_ccm->CCGR4);
105 void set_usb_phy2_clk(void)
109 reg = readl(&mxc_ccm->cscmr1);
110 reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
111 writel(reg, &mxc_ccm->cscmr1);
114 void enable_usb_phy2_clk(unsigned char enable)
118 reg = readl(&mxc_ccm->CCGR4);
120 reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
122 reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
123 writel(reg, &mxc_ccm->CCGR4);
127 * Calculate the frequency of PLLn.
129 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
131 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
132 uint64_t refclk, temp;
135 ctrl = readl(&pll->ctrl);
137 if (ctrl & MXC_DPLLC_CTL_HFSM) {
138 mfn = __raw_readl(&pll->hfs_mfn);
139 mfd = __raw_readl(&pll->hfs_mfd);
140 op = __raw_readl(&pll->hfs_op);
142 mfn = __raw_readl(&pll->mfn);
143 mfd = __raw_readl(&pll->mfd);
144 op = __raw_readl(&pll->op);
147 mfd &= MXC_DPLLC_MFD_MFD_MASK;
148 mfn &= MXC_DPLLC_MFN_MFN_MASK;
149 pdf = op & MXC_DPLLC_OP_PDF_MASK;
150 mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
157 if (mfn >= 0x04000000) {
164 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
167 do_div(refclk, pdf + 1);
168 temp = refclk * mfn_abs;
169 do_div(temp, mfd + 1);
183 u32 get_mcu_main_clk(void)
187 reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
188 MXC_CCM_CACRR_ARM_PODF_OFFSET;
189 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
190 return freq / (reg + 1);
194 * Get the rate of peripheral's root clock.
196 u32 get_periph_clk(void)
200 reg = __raw_readl(&mxc_ccm->cbcdr);
201 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
202 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
203 reg = __raw_readl(&mxc_ccm->cbcmr);
204 switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
205 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
207 return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
209 return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
217 * Get the rate of ipg clock.
219 static u32 get_ipg_clk(void)
221 uint32_t freq, reg, div;
223 freq = get_ahb_clk();
225 reg = __raw_readl(&mxc_ccm->cbcdr);
226 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
227 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
233 * Get the rate of ipg_per clock.
235 static u32 get_ipg_per_clk(void)
237 u32 pred1, pred2, podf;
239 if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
240 return get_ipg_clk();
241 /* Fixme: not handle what about lpm*/
242 podf = __raw_readl(&mxc_ccm->cbcdr);
243 pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
244 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
245 pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
246 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
247 podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
248 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
250 return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
254 * Get the rate of uart clk.
256 static u32 get_uart_clk(void)
258 unsigned int freq, reg, pred, podf;
260 reg = __raw_readl(&mxc_ccm->cscmr1);
261 switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
262 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
264 freq = decode_pll(mxc_plls[PLL1_CLOCK],
265 CONFIG_SYS_MX5_HCLK);
268 freq = decode_pll(mxc_plls[PLL2_CLOCK],
269 CONFIG_SYS_MX5_HCLK);
272 freq = decode_pll(mxc_plls[PLL3_CLOCK],
273 CONFIG_SYS_MX5_HCLK);
279 reg = __raw_readl(&mxc_ccm->cscdr1);
281 pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
282 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
284 podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
285 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
286 freq /= (pred + 1) * (podf + 1);
292 * This function returns the low power audio clock.
297 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
299 if (((ccsr >> 9) & 1) == 0)
300 ret_val = CONFIG_SYS_MX5_HCLK;
302 ret_val = ((32768 * 1024));
308 * get cspi clock rate.
310 u32 imx_get_cspiclk(void)
312 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
313 u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
314 u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
316 pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
317 >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
318 pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
319 >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
320 clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
321 >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
325 ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
326 CONFIG_SYS_MX5_HCLK) /
327 ((pre_pdf + 1) * (pdf + 1));
330 ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
331 CONFIG_SYS_MX5_HCLK) /
332 ((pre_pdf + 1) * (pdf + 1));
335 ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
336 CONFIG_SYS_MX5_HCLK) /
337 ((pre_pdf + 1) * (pdf + 1));
340 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
348 * The API of get mxc clockes.
350 unsigned int mxc_get_clock(enum mxc_clock clk)
354 return get_mcu_main_clk();
356 return get_ahb_clk();
358 return get_ipg_clk();
360 return get_ipg_per_clk();
362 return get_uart_clk();
364 return imx_get_cspiclk();
366 return decode_pll(mxc_plls[PLL1_CLOCK],
367 CONFIG_SYS_MX5_HCLK);
369 return get_ahb_clk();
376 u32 imx_get_uartclk(void)
378 return get_uart_clk();
382 u32 imx_get_fecclk(void)
384 return mxc_get_clock(MXC_IPG_CLK);
389 * The clock for the external interface can be set to use internal clock
390 * if fuse bank 4, row 3, bit 2 is set.
391 * This is an undocumented feature and it was confirmed by Freescale's support:
392 * Fuses (but not pins) may be used to configure SATA clocks.
393 * Particularly the i.MX53 Fuse_Map contains the next information
394 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
395 * '00' - 100MHz (External)
396 * '01' - 50MHz (External)
397 * '10' - 120MHz, internal (USB PHY)
400 void mxc_set_sata_internal_clock(void)
403 (u32 *)(IIM_BASE_ADDR + 0x180c);
407 writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
412 * Dump some core clockes.
414 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
418 freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
419 printf("PLL1 %8d MHz\n", freq / 1000000);
420 freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
421 printf("PLL2 %8d MHz\n", freq / 1000000);
422 freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
423 printf("PLL3 %8d MHz\n", freq / 1000000);
425 freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
426 printf("PLL4 %8d MHz\n", freq / 1000000);
430 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
431 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
432 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
437 /***************************************************/
440 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,