3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/errno.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/crm_regs.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
45 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
46 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
47 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
48 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
50 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
54 #define AHB_CLK_ROOT 133333333
55 #define SZ_DEC_1M 1000000
56 #define PLL_PD_MAX 16 /* Actual pd+1 */
57 #define PLL_MFI_MAX 15
65 #define MX5_CBCMR 0x00015154
66 #define MX5_CBCDR 0x02888945
68 struct fixed_pll_mfd {
73 const struct fixed_pll_mfd fixed_mfd[] = {
84 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
85 #define PLL_FREQ_MIN(ref_clk) \
86 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
87 #define MAX_DDR_CLK 420000000
88 #define NFC_CLK_MAX 34000000
90 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
92 void set_usboh3_clk(void)
94 clrsetbits_le32(&mxc_ccm->cscmr1,
95 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
96 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
97 clrsetbits_le32(&mxc_ccm->cscdr1,
98 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
99 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
100 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
101 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
104 void enable_usboh3_clk(unsigned char enable)
106 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
108 clrsetbits_le32(&mxc_ccm->CCGR2,
109 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
110 MXC_CCM_CCGR2_USBOH3_60M(cg));
113 #ifdef CONFIG_I2C_MXC
114 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
115 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
119 #if defined(CONFIG_MX51)
121 #elif defined(CONFIG_MX53)
125 mask = MXC_CCM_CCGR_CG_MASK <<
126 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
128 setbits_le32(&mxc_ccm->CCGR1, mask);
130 clrbits_le32(&mxc_ccm->CCGR1, mask);
135 void set_usb_phy_clk(void)
137 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
140 #if defined(CONFIG_MX51)
141 void enable_usb_phy1_clk(unsigned char enable)
143 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
145 clrsetbits_le32(&mxc_ccm->CCGR2,
146 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
147 MXC_CCM_CCGR2_USB_PHY(cg));
150 void enable_usb_phy2_clk(unsigned char enable)
152 /* i.MX51 has a single USB PHY clock, so do nothing here. */
154 #elif defined(CONFIG_MX53)
155 void enable_usb_phy1_clk(unsigned char enable)
157 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
159 clrsetbits_le32(&mxc_ccm->CCGR4,
160 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
161 MXC_CCM_CCGR4_USB_PHY1(cg));
164 void enable_usb_phy2_clk(unsigned char enable)
166 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
168 clrsetbits_le32(&mxc_ccm->CCGR4,
169 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
170 MXC_CCM_CCGR4_USB_PHY2(cg));
175 * Calculate the frequency of PLLn.
177 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
179 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
180 uint64_t refclk, temp;
183 ctrl = readl(&pll->ctrl);
185 if (ctrl & MXC_DPLLC_CTL_HFSM) {
186 mfn = readl(&pll->hfs_mfn);
187 mfd = readl(&pll->hfs_mfd);
188 op = readl(&pll->hfs_op);
190 mfn = readl(&pll->mfn);
191 mfd = readl(&pll->mfd);
192 op = readl(&pll->op);
195 mfd &= MXC_DPLLC_MFD_MFD_MASK;
196 mfn &= MXC_DPLLC_MFN_MFN_MASK;
197 pdf = op & MXC_DPLLC_OP_PDF_MASK;
198 mfi = MXC_DPLLC_OP_MFI_RD(op);
205 if (mfn >= 0x04000000) {
212 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
215 do_div(refclk, pdf + 1);
216 temp = refclk * mfn_abs;
217 do_div(temp, mfd + 1);
230 * This function returns the Frequency Pre-Multiplier clock.
232 static u32 get_fpm(void)
235 u32 ccr = readl(&mxc_ccm->ccr);
237 if (ccr & MXC_CCM_CCR_FPM_MULT)
242 return MXC_CLK32 * mult;
247 * This function returns the low power audio clock.
249 static u32 get_lp_apm(void)
252 u32 ccsr = readl(&mxc_ccm->ccsr);
254 if (ccsr & MXC_CCM_CCSR_LP_APM)
255 #if defined(CONFIG_MX51)
257 #elif defined(CONFIG_MX53)
258 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
269 u32 get_mcu_main_clk(void)
273 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
274 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
275 return freq / (reg + 1);
279 * Get the rate of peripheral's root clock.
281 u32 get_periph_clk(void)
285 reg = readl(&mxc_ccm->cbcdr);
286 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
287 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
288 reg = readl(&mxc_ccm->cbcmr);
289 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
291 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
293 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
303 * Get the rate of ipg clock.
305 static u32 get_ipg_clk(void)
307 uint32_t freq, reg, div;
309 freq = get_ahb_clk();
311 reg = readl(&mxc_ccm->cbcdr);
312 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
318 * Get the rate of ipg_per clock.
320 static u32 get_ipg_per_clk(void)
322 u32 freq, pred1, pred2, podf;
324 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
325 return get_ipg_clk();
327 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
330 freq = get_periph_clk();
331 podf = readl(&mxc_ccm->cbcdr);
332 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
333 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
334 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
335 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
338 /* Get the output clock rate of a standard PLL MUX for peripherals. */
339 static u32 get_standard_pll_sel_clk(u32 clk_sel)
343 switch (clk_sel & 0x3) {
345 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
348 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
351 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
362 * Get the rate of uart clk.
364 static u32 get_uart_clk(void)
366 unsigned int clk_sel, freq, reg, pred, podf;
368 reg = readl(&mxc_ccm->cscmr1);
369 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
370 freq = get_standard_pll_sel_clk(clk_sel);
372 reg = readl(&mxc_ccm->cscdr1);
373 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
374 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
375 freq /= (pred + 1) * (podf + 1);
381 * get cspi clock rate.
383 static u32 imx_get_cspiclk(void)
385 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
386 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
387 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
389 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
390 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
391 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
392 freq = get_standard_pll_sel_clk(clk_sel);
393 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
398 * get esdhc clock rate.
400 static u32 get_esdhc_clk(u32 port)
402 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
403 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
404 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
408 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
409 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
410 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
413 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
414 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
415 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
418 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
419 return get_esdhc_clk(1);
421 return get_esdhc_clk(0);
423 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
424 return get_esdhc_clk(1);
426 return get_esdhc_clk(0);
431 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
435 static u32 get_axi_a_clk(void)
437 u32 cbcdr = readl(&mxc_ccm->cbcdr);
438 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
440 return get_periph_clk() / (pdf + 1);
443 static u32 get_axi_b_clk(void)
445 u32 cbcdr = readl(&mxc_ccm->cbcdr);
446 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
448 return get_periph_clk() / (pdf + 1);
451 static u32 get_emi_slow_clk(void)
453 u32 cbcdr = readl(&mxc_ccm->cbcdr);
454 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
455 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
458 return get_ahb_clk() / (pdf + 1);
460 return get_periph_clk() / (pdf + 1);
463 static u32 get_ddr_clk(void)
466 u32 cbcmr = readl(&mxc_ccm->cbcmr);
467 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
469 u32 cbcdr = readl(&mxc_ccm->cbcdr);
470 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
471 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
473 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
474 ret_val /= ddr_clk_podf + 1;
479 switch (ddr_clk_sel) {
481 ret_val = get_axi_a_clk();
484 ret_val = get_axi_b_clk();
487 ret_val = get_emi_slow_clk();
490 ret_val = get_ahb_clk();
500 * The API of get mxc clocks.
502 unsigned int mxc_get_clock(enum mxc_clock clk)
506 return get_mcu_main_clk();
508 return get_ahb_clk();
510 return get_ipg_clk();
513 return get_ipg_per_clk();
515 return get_uart_clk();
517 return imx_get_cspiclk();
519 return get_esdhc_clk(0);
521 return get_esdhc_clk(1);
523 return get_esdhc_clk(2);
525 return get_esdhc_clk(3);
527 return get_ipg_clk();
529 return get_ahb_clk();
531 return get_ddr_clk();
538 u32 imx_get_uartclk(void)
540 return get_uart_clk();
543 u32 imx_get_fecclk(void)
545 return get_ipg_clk();
548 static int gcd(int m, int n)
563 * This is to calculate various parameters based on reference clock and
564 * targeted clock based on the equation:
565 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
566 * This calculation is based on a fixed MFD value for simplicity.
568 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
570 u64 pd, mfi = 1, mfn, mfd, t1;
571 u32 n_target = target;
575 * Make sure targeted freq is in the valid range.
576 * Otherwise the following calculation might be wrong!!!
578 if (n_target < PLL_FREQ_MIN(ref) ||
579 n_target > PLL_FREQ_MAX(ref)) {
580 printf("Targeted peripheral clock should be"
581 "within [%d - %d]\n",
582 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
583 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
587 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
588 if (fixed_mfd[i].ref_clk_hz == ref) {
589 mfd = fixed_mfd[i].mfd;
594 if (i == ARRAY_SIZE(fixed_mfd))
597 /* Use n_target and n_ref to avoid overflow */
598 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
600 do_div(t1, (4 * n_ref));
602 if (mfi > PLL_MFI_MAX)
609 * Now got pd and mfi already
611 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
619 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
620 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
634 #define calc_div(tgt_clk, src_clk, limit) ({ \
636 if (((src_clk) % (tgt_clk)) <= 100) \
637 v = (src_clk) / (tgt_clk); \
639 v = ((src_clk) / (tgt_clk)) + 1;\
645 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
647 writel(0x1232, &pll->ctrl); \
648 writel(0x2, &pll->config); \
649 writel((((pd) - 1) << 0) | ((fi) << 4), \
651 writel(fn, &(pll->mfn)); \
652 writel((fd) - 1, &pll->mfd); \
653 writel((((pd) - 1) << 0) | ((fi) << 4), \
655 writel(fn, &pll->hfs_mfn); \
656 writel((fd) - 1, &pll->hfs_mfd); \
657 writel(0x1232, &pll->ctrl); \
658 while (!readl(&pll->ctrl) & 0x1) \
662 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
664 u32 ccsr = readl(&mxc_ccm->ccsr);
665 struct mxc_pll_reg *pll = mxc_plls[index];
669 /* Switch ARM to PLL2 clock */
670 writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
672 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
673 pll_param->mfi, pll_param->mfn,
676 writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
680 /* Switch to pll2 bypass clock */
681 writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
683 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
684 pll_param->mfi, pll_param->mfn,
687 writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
691 /* Switch to pll3 bypass clock */
692 writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
694 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
695 pll_param->mfi, pll_param->mfn,
698 writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
703 /* Switch to pll4 bypass clock */
704 writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
706 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
707 pll_param->mfi, pll_param->mfn,
710 writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
721 /* Config CPU clock */
722 static int config_core_clk(u32 ref, u32 freq)
725 struct pll_param pll_param;
727 memset(&pll_param, 0, sizeof(struct pll_param));
729 /* The case that periph uses PLL1 is not considered here */
730 ret = calc_pll_params(ref, freq, &pll_param);
732 printf("Error:Can't find pll parameters: %d\n", ret);
736 return config_pll_clk(PLL1_CLOCK, &pll_param);
739 static int config_nfc_clk(u32 nfc_clk)
741 u32 parent_rate = get_emi_slow_clk();
742 u32 div = parent_rate / nfc_clk;
748 if (parent_rate / div > NFC_CLK_MAX)
750 clrsetbits_le32(&mxc_ccm->cbcdr,
751 MXC_CCM_CBCDR_NFC_PODF_MASK,
752 MXC_CCM_CBCDR_NFC_PODF(div - 1));
753 while (readl(&mxc_ccm->cdhipr) != 0)
758 /* Config main_bus_clock for periphs */
759 static int config_periph_clk(u32 ref, u32 freq)
762 struct pll_param pll_param;
764 memset(&pll_param, 0, sizeof(struct pll_param));
766 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
767 ret = calc_pll_params(ref, freq, &pll_param);
769 printf("Error:Can't find pll parameters: %d\n",
773 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
774 readl(&mxc_ccm->cbcmr))) {
776 return config_pll_clk(PLL1_CLOCK, &pll_param);
779 return config_pll_clk(PLL3_CLOCK, &pll_param);
789 static int config_ddr_clk(u32 emi_clk)
792 s32 shift = 0, clk_sel, div = 1;
793 u32 cbcmr = readl(&mxc_ccm->cbcmr);
795 if (emi_clk > MAX_DDR_CLK) {
796 printf("Warning:DDR clock should not exceed %d MHz\n",
797 MAX_DDR_CLK / SZ_DEC_1M);
798 emi_clk = MAX_DDR_CLK;
801 clk_src = get_periph_clk();
802 /* Find DDR clock input */
803 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
821 if ((clk_src % emi_clk) < 10000000)
822 div = clk_src / emi_clk;
824 div = (clk_src / emi_clk) + 1;
828 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
829 while (readl(&mxc_ccm->cdhipr) != 0)
831 writel(0x0, &mxc_ccm->ccdr);
837 * This function assumes the expected core clock has to be changed by
838 * modifying the PLL. This is NOT true always but for most of the times,
839 * it is. So it assumes the PLL output freq is the same as the expected
840 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
841 * In the latter case, it will try to increase the presc value until
842 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
843 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
844 * on the targeted PLL and reference input clock to the PLL. Lastly,
845 * it sets the register based on these values along with the dividers.
846 * Note 1) There is no value checking for the passed-in divider values
847 * so the caller has to make sure those values are sensible.
848 * 2) Also adjust the NFC divider such that the NFC clock doesn't
849 * exceed NFC_CLK_MAX.
850 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
851 * 177MHz for higher voltage, this function fixes the max to 133MHz.
852 * 4) This function should not have allowed diag_printf() calls since
853 * the serial driver has been stoped. But leave then here to allow
854 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
856 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
862 if (config_core_clk(ref, freq))
866 if (config_periph_clk(ref, freq))
870 if (config_ddr_clk(freq))
874 if (config_nfc_clk(freq))
878 printf("Warning:Unsupported or invalid clock type\n");
886 * The clock for the external interface can be set to use internal clock
887 * if fuse bank 4, row 3, bit 2 is set.
888 * This is an undocumented feature and it was confirmed by Freescale's support:
889 * Fuses (but not pins) may be used to configure SATA clocks.
890 * Particularly the i.MX53 Fuse_Map contains the next information
891 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
892 * '00' - 100MHz (External)
893 * '01' - 50MHz (External)
894 * '10' - 120MHz, internal (USB PHY)
897 void mxc_set_sata_internal_clock(void)
900 (u32 *)(IIM_BASE_ADDR + 0x180c);
904 clrsetbits_le32(tmp_base, 0x6, 0x4);
909 * Dump some core clockes.
911 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
915 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
916 printf("PLL1 %8d MHz\n", freq / 1000000);
917 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
918 printf("PLL2 %8d MHz\n", freq / 1000000);
919 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
920 printf("PLL3 %8d MHz\n", freq / 1000000);
922 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
923 printf("PLL4 %8d MHz\n", freq / 1000000);
927 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
928 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
929 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
930 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
935 /***************************************************/
938 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,