2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ls102xa_soc.h>
13 unsigned int get_soc_major_rev(void)
15 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
16 unsigned int svr, major;
18 svr = in_be32(&gur->svr);
24 int arch_soc_init(void)
26 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
27 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
30 #ifdef CONFIG_FSL_QSPI
31 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
34 #ifdef CONFIG_FSL_DCU_FB
35 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
38 /* Configure Little endian for SAI, ASRC and SPDIF */
39 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
42 * Enable snoop requests and DVM message requests for
43 * All the slave insterfaces.
45 out_le32(&cci->slave[0].snoop_ctrl,
46 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
47 out_le32(&cci->slave[1].snoop_ctrl,
48 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
49 out_le32(&cci->slave[2].snoop_ctrl,
50 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
51 out_le32(&cci->slave[4].snoop_ctrl,
52 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
54 major = get_soc_major_rev();
55 if (major == SOC_MAJOR_VER_1_0) {
57 * Set CCI-400 Slave interface S1, S2 Shareable Override
58 * Register All transactions are treated as non-shareable
60 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
61 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
63 /* Workaround for the issue that DDR could not respond to
64 * barrier transaction which is generated by executing DSB/ISB
65 * instruction. Set CCI-400 control override register to
66 * terminate the barrier transaction. After DDR is initialized,
67 * allow barrier transaction to DDR again */
68 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
71 /* Enable all the snoop signal for various masters */
72 out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
73 SCFG_SNPCNFGCR_DCU_RD_WR |
74 SCFG_SNPCNFGCR_SATA_RD_WR |
75 SCFG_SNPCNFGCR_USB3_RD_WR |
76 SCFG_SNPCNFGCR_DBG_RD_WR |
77 SCFG_SNPCNFGCR_EDMA_SNP);
80 * Memory controller require a register write before being enabled.
83 * Description: Memory controller performance is not optimal with
84 * default internal target queue register values.
85 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
87 out_be32(&scfg->eddrtqcfg, 0x63b20042);