arch/arm/cpu/armv7/ls102xa/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <fsl_csu.h>
  15
  16 struct liodn_id_table sec_liodn_tbl[] = {
  17         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  18         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  19         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  20         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  21         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  23         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  24         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  25         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  31         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  32         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  33 };
  34
  35 struct smmu_stream_id dev_stream_id[] = {
  36         { 0x100, 0x01, "ETSEC MAC1" },
  37         { 0x104, 0x02, "ETSEC MAC2" },
  38         { 0x108, 0x03, "ETSEC MAC3" },
  39         { 0x10c, 0x04, "PEX1" },
  40         { 0x110, 0x05, "PEX2" },
  41         { 0x114, 0x06, "qDMA" },
  42         { 0x118, 0x07, "SATA" },
  43         { 0x11c, 0x08, "USB3" },
  44         { 0x120, 0x09, "QE" },
  45         { 0x124, 0x0a, "eSDHC" },
  46         { 0x128, 0x0b, "eMA" },
  47         { 0x14c, 0x0c, "2D-ACE" },
  48         { 0x150, 0x0d, "USB2" },
  49         { 0x18c, 0x0e, "DEBUG" },
  50 };
  51
  52 unsigned int get_soc_major_rev(void)
  53 {
  54         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  55         unsigned int svr, major;
  56
  57         svr = in_be32(&gur->svr);
  58         major = SVR_MAJ(svr);
  59
  60         return major;
  61 }
  62
  63 static void erratum_a009008(void)
  64 {
  65 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  66         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  67
  68         clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  69                         0xF << 6,
  70                         SCFG_USB_TXVREFTUNE << 6);
  71 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  72 }
  73
  74 static void erratum_a009798(void)
  75 {
  76 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  77         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  78
  79         clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  80                         SCFG_USB_SQRXTUNE_MASK << 23);
  81 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  82 }
  83
  84 static void erratum_a008997(void)
  85 {
  86 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  87         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  88
  89         clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
  90                         SCFG_USB_PCSTXSWINGFULL_MASK,
  91                         SCFG_USB_PCSTXSWINGFULL_VAL);
  92 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  93 }
  94
  95 static void erratum_a009007(void)
  96 {
  97 #ifdef CONFIG_SYS_FSL_ERRATUM_A009007
  98         void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
  99
 100         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
 101         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
 102         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
 103         out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
 104 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
 105 }
 106
 107 void s_init(void)
 108 {
 109 }
 110
 111 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 112 void erratum_a010315(void)
 113 {
 114         int i;
 115
 116         for (i = PCIE1; i <= PCIE2; i++)
 117                 if (!is_serdes_configured(i)) {
 118                         debug("PCIe%d: disabled all R/W permission!\n", i);
 119                         set_pcie_ns_access(i, 0);
 120                 }
 121 }
 122 #endif
 123
 124 int arch_soc_init(void)
 125 {
 126         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 127         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 128                                         CONFIG_SYS_CCI400_OFFSET);
 129         unsigned int major;
 130
 131 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 132         enable_layerscape_ns_access();
 133 #endif
 134
 135 #ifdef CONFIG_FSL_QSPI
 136         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 137 #endif
 138
 139 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 140         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 141 #endif
 142
 143         /* Configure Little endian for SAI, ASRC and SPDIF */
 144         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 145
 146         /*
 147          * Enable snoop requests and DVM message requests for
 148          * All the slave insterfaces.
 149          */
 150         out_le32(&cci->slave[0].snoop_ctrl,
 151                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 152         out_le32(&cci->slave[1].snoop_ctrl,
 153                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 154         out_le32(&cci->slave[2].snoop_ctrl,
 155                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 156         out_le32(&cci->slave[4].snoop_ctrl,
 157                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 158
 159         major = get_soc_major_rev();
 160         if (major == SOC_MAJOR_VER_1_0) {
 161                 /*
 162                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 163                  * Register All transactions are treated as non-shareable
 164                  */
 165                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 166                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 167
 168                 /* Workaround for the issue that DDR could not respond to
 169                  * barrier transaction which is generated by executing DSB/ISB
 170                  * instruction. Set CCI-400 control override register to
 171                  * terminate the barrier transaction. After DDR is initialized,
 172                  * allow barrier transaction to DDR again */
 173                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 174         }
 175
 176         /* Enable all the snoop signal for various masters */
 177         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 178                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 179                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 180                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 181                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 182                                 SCFG_SNPCNFGCR_EDMA_SNP);
 183
 184         /*
 185          * Memory controller require a register write before being enabled.
 186          * Affects: DDR
 187          * Register: EDDRTQCFG
 188          * Description: Memory controller performance is not optimal with
 189          *              default internal target queue register values.
 190          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 191          */
 192         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 193
 194         /* Erratum */
 195         erratum_a009008();
 196         erratum_a009798();
 197         erratum_a008997();
 198         erratum_a009007();
 199
 200         return 0;
 201 }
 202
 203 int ls102xa_smmu_stream_id_init(void)
 204 {
 205         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 206                                       ARRAY_SIZE(sec_liodn_tbl));
 207
 208         ls102xa_config_smmu_stream_id(dev_stream_id,
 209                                       ARRAY_SIZE(dev_stream_id));
 210
 211         return 0;
 212 }