arch/arm/cpu/armv7/ls102xa/soc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch/immap_ls102xa.h>
  12 #include <asm/arch/ls102xa_soc.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <fsl_csu.h>
  15
  16 struct liodn_id_table sec_liodn_tbl[] = {
  17         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  18         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  19         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  20         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  21         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  22         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  23         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  24         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  25         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  26         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  27         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  28         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  29         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  30         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  31         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  32         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  33 };
  34
  35 struct smmu_stream_id dev_stream_id[] = {
  36         { 0x100, 0x01, "ETSEC MAC1" },
  37         { 0x104, 0x02, "ETSEC MAC2" },
  38         { 0x108, 0x03, "ETSEC MAC3" },
  39         { 0x10c, 0x04, "PEX1" },
  40         { 0x110, 0x05, "PEX2" },
  41         { 0x114, 0x06, "qDMA" },
  42         { 0x118, 0x07, "SATA" },
  43         { 0x11c, 0x08, "USB3" },
  44         { 0x120, 0x09, "QE" },
  45         { 0x124, 0x0a, "eSDHC" },
  46         { 0x128, 0x0b, "eMA" },
  47         { 0x14c, 0x0c, "2D-ACE" },
  48         { 0x150, 0x0d, "USB2" },
  49         { 0x18c, 0x0e, "DEBUG" },
  50 };
  51
  52 unsigned int get_soc_major_rev(void)
  53 {
  54         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  55         unsigned int svr, major;
  56
  57         svr = in_be32(&gur->svr);
  58         major = SVR_MAJ(svr);
  59
  60         return major;
  61 }
  62
  63 static void erratum_a009008(void)
  64 {
  65 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  66         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  67
  68         clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  69                         0xF << 6,
  70                         SCFG_USB_TXVREFTUNE << 6);
  71 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  72 }
  73
  74 static void erratum_a009798(void)
  75 {
  76 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  77         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  78
  79         clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  80                         SCFG_USB_SQRXTUNE_MASK << 23);
  81 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  82 }
  83
  84 static void erratum_a008997(void)
  85 {
  86 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  87         u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  88
  89         clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
  90                         SCFG_USB_PCSTXSWINGFULL_MASK,
  91                         SCFG_USB_PCSTXSWINGFULL_VAL);
  92 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  93 }
  94
  95
  96 void s_init(void)
  97 {
  98 }
  99
 100 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 101 void erratum_a010315(void)
 102 {
 103         int i;
 104
 105         for (i = PCIE1; i <= PCIE2; i++)
 106                 if (!is_serdes_configured(i)) {
 107                         debug("PCIe%d: disabled all R/W permission!\n", i);
 108                         set_pcie_ns_access(i, 0);
 109                 }
 110 }
 111 #endif
 112
 113 int arch_soc_init(void)
 114 {
 115         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 116         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 117                                         CONFIG_SYS_CCI400_OFFSET);
 118         unsigned int major;
 119
 120 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 121         enable_layerscape_ns_access();
 122 #endif
 123
 124 #ifdef CONFIG_FSL_QSPI
 125         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 126 #endif
 127
 128 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 129         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 130 #endif
 131
 132         /* Configure Little endian for SAI, ASRC and SPDIF */
 133         out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 134
 135         /*
 136          * Enable snoop requests and DVM message requests for
 137          * All the slave insterfaces.
 138          */
 139         out_le32(&cci->slave[0].snoop_ctrl,
 140                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 141         out_le32(&cci->slave[1].snoop_ctrl,
 142                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 143         out_le32(&cci->slave[2].snoop_ctrl,
 144                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 145         out_le32(&cci->slave[4].snoop_ctrl,
 146                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 147
 148         major = get_soc_major_rev();
 149         if (major == SOC_MAJOR_VER_1_0) {
 150                 /*
 151                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 152                  * Register All transactions are treated as non-shareable
 153                  */
 154                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 155                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 156
 157                 /* Workaround for the issue that DDR could not respond to
 158                  * barrier transaction which is generated by executing DSB/ISB
 159                  * instruction. Set CCI-400 control override register to
 160                  * terminate the barrier transaction. After DDR is initialized,
 161                  * allow barrier transaction to DDR again */
 162                 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 163         }
 164
 165         /* Enable all the snoop signal for various masters */
 166         out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 167                                 SCFG_SNPCNFGCR_DCU_RD_WR |
 168                                 SCFG_SNPCNFGCR_SATA_RD_WR |
 169                                 SCFG_SNPCNFGCR_USB3_RD_WR |
 170                                 SCFG_SNPCNFGCR_DBG_RD_WR |
 171                                 SCFG_SNPCNFGCR_EDMA_SNP);
 172
 173         /*
 174          * Memory controller require a register write before being enabled.
 175          * Affects: DDR
 176          * Register: EDDRTQCFG
 177          * Description: Memory controller performance is not optimal with
 178          *              default internal target queue register values.
 179          * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 180          */
 181         out_be32(&scfg->eddrtqcfg, 0x63b20042);
 182
 183         /* Erratum */
 184         erratum_a009008();
 185         erratum_a009798();
 186         erratum_a008997();
 187
 188         return 0;
 189 }
 190
 191 int ls102xa_smmu_stream_id_init(void)
 192 {
 193         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 194                                       ARRAY_SIZE(sec_liodn_tbl));
 195
 196         ls102xa_config_smmu_stream_id(dev_stream_id,
 197                                       ARRAY_SIZE(dev_stream_id));
 198
 199         return 0;
 200 }