1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
11 #define FSL_STRIDE_4B 4
12 #define FSL_STRIDE_8B 8
15 #define EPU_BLOCK_OFFSET 0x00000000
17 /* EPGCR (Event Processor Global Control Register) */
20 /* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
21 #define EPEVTCR0 0x050
22 #define EPEVTCR9 0x074
23 #define EPEVTCR_STRIDE FSL_STRIDE_4B
25 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
26 #define EPXTRIGCR 0x090
28 /* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
30 #define EPIMCR31 0x17C
31 #define EPIMCR_STRIDE FSL_STRIDE_4B
33 /* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
35 #define EPSMCR15 0x278
36 #define EPSMCR_STRIDE FSL_STRIDE_8B
38 /* EPECR0-15 (Event Processor Event Control Registers) */
41 #define EPECR_STRIDE FSL_STRIDE_4B
43 /* EPACR0-15 (Event Processor Action Control Registers) */
46 #define EPACR_STRIDE FSL_STRIDE_4B
48 /* EPCCRi0-15 (Event Processor Counter Control Registers) */
52 #define EPCCR_STRIDE FSL_STRIDE_4B
54 /* EPCMPR0-15 (Event Processor Counter Compare Registers) */
56 #define EPCMPR15 0x93C
57 #define EPCMPR31 0x97C
58 #define EPCMPR_STRIDE FSL_STRIDE_4B
60 /* EPCTR0-31 (Event Processor Counter Register) */
63 #define EPCTR_STRIDE FSL_STRIDE_4B
65 #define FSM_END_FLAG 0xFFFFFFFFUL
72 void fsl_epu_setup(void *epu_base);
73 void fsl_epu_clean(void *epu_base);