3 select SYS_FSL_DDR_BE if SYS_FSL_DDR
4 select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
5 select SYS_FSL_ERRATUM_A008378
6 select SYS_FSL_ERRATUM_A008407
7 select SYS_FSL_ERRATUM_A008850
8 select SYS_FSL_ERRATUM_A008997
9 select SYS_FSL_ERRATUM_A009007
10 select SYS_FSL_ERRATUM_A009008
11 select SYS_FSL_ERRATUM_A009663
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A009942
14 select SYS_FSL_ERRATUM_A010315
15 select SYS_FSL_HAS_CCI400
16 select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
17 select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
18 select SYS_FSL_HAS_SEC
19 select SYS_FSL_SEC_COMPAT_5
27 menu "LS102xA architecture"
28 depends on ARCH_LS1021A
30 config FSL_PCIE_COMPAT
31 string "PCIe compatible of Kernel DT"
32 depends on PCIE_LAYERSCAPE
33 default "fsl,ls1021a-pcie" if ARCH_LS1021A
35 This compatible is used to find pci controller node in Kernel DT
40 depends on ARCH_LS1021A
43 int "Maximum number of CPUs permitted for LS102xA"
44 depends on ARCH_LS1021A
47 Set this number to the maximum number of possible CPUs in the SoC.
48 SoCs may have multiple clusters with each cluster may have multiple
49 ports. If some ports are reserved but higher ports are used for
50 cores, count the reserved ports. This will allocate enough memory
51 in spin table to properly handle all cores.
56 Enable Freescale Secure Boot feature. Normally selected
57 by defconfig. If unsure, do not change.
59 config SYS_CCI400_OFFSET
60 hex "Offset for CCI400 base"
61 depends on SYS_FSL_HAS_CCI400
64 Offset for CCI400 base.
65 CCI400 base addr = CCSRBAR + CCI400_OFFSET
67 config SYS_FSL_ERRATUM_A008850
70 Workaround for DDR erratum A008850
72 config SYS_FSL_ERRATUM_A008997
75 Workaround for USB PHY erratum A008997
77 config SYS_FSL_ERRATUM_A009007
80 Workaround for USB PHY erratum A009007
82 config SYS_FSL_ERRATUM_A009008
85 Workaround for USB PHY erratum A009008
87 config SYS_FSL_ERRATUM_A009798
90 Workaround for USB PHY erratum A009798
92 config SYS_FSL_ERRATUM_A010315
93 bool "Workaround for PCIe erratum A010315"
95 config SYS_FSL_HAS_CCI400
101 config SYS_FSL_SRDS_2
104 config SYS_HAS_SERDES
107 config SYS_FSL_IFC_BANK_COUNT
108 int "Maximum banks of Integrated flash controller"
109 depends on ARCH_LS1021A
112 config SYS_FSL_ERRATUM_A008407