2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/periph.h>
14 #define PLL_DIV_1024 1024
15 #define PLL_DIV_65535 65535
16 #define PLL_DIV_65536 65536
19 * This structure is to store the src bit, div bit and prediv bit
20 * positions of the peripheral clocks of the src and div registers
29 /* periph_id src_bit div_bit prediv_bit */
30 static struct clk_bit_info exynos5_bit_info[] = {
31 {PERIPH_ID_UART0, 0, 0, -1},
32 {PERIPH_ID_UART1, 4, 4, -1},
33 {PERIPH_ID_UART2, 8, 8, -1},
34 {PERIPH_ID_UART3, 12, 12, -1},
35 {PERIPH_ID_I2C0, -1, 24, 0},
36 {PERIPH_ID_I2C1, -1, 24, 0},
37 {PERIPH_ID_I2C2, -1, 24, 0},
38 {PERIPH_ID_I2C3, -1, 24, 0},
39 {PERIPH_ID_I2C4, -1, 24, 0},
40 {PERIPH_ID_I2C5, -1, 24, 0},
41 {PERIPH_ID_I2C6, -1, 24, 0},
42 {PERIPH_ID_I2C7, -1, 24, 0},
43 {PERIPH_ID_SPI0, 16, 0, 8},
44 {PERIPH_ID_SPI1, 20, 16, 24},
45 {PERIPH_ID_SPI2, 24, 0, 8},
46 {PERIPH_ID_SDMMC0, 0, 0, 8},
47 {PERIPH_ID_SDMMC1, 4, 16, 24},
48 {PERIPH_ID_SDMMC2, 8, 0, 8},
49 {PERIPH_ID_SDMMC3, 12, 16, 24},
50 {PERIPH_ID_I2S0, 0, 0, 4},
51 {PERIPH_ID_I2S1, 4, 12, 16},
52 {PERIPH_ID_SPI3, 0, 0, 4},
53 {PERIPH_ID_SPI4, 4, 12, 16},
54 {PERIPH_ID_SDMMC4, 16, 0, 8},
55 {PERIPH_ID_PWM0, 24, 0, -1},
56 {PERIPH_ID_PWM1, 24, 0, -1},
57 {PERIPH_ID_PWM2, 24, 0, -1},
58 {PERIPH_ID_PWM3, 24, 0, -1},
59 {PERIPH_ID_PWM4, 24, 0, -1},
61 {PERIPH_ID_NONE, -1, -1, -1},
64 static struct clk_bit_info exynos542x_bit_info[] = {
65 {PERIPH_ID_UART0, 4, 8, -1},
66 {PERIPH_ID_UART1, 8, 12, -1},
67 {PERIPH_ID_UART2, 12, 16, -1},
68 {PERIPH_ID_UART3, 16, 20, -1},
69 {PERIPH_ID_I2C0, -1, 8, -1},
70 {PERIPH_ID_I2C1, -1, 8, -1},
71 {PERIPH_ID_I2C2, -1, 8, -1},
72 {PERIPH_ID_I2C3, -1, 8, -1},
73 {PERIPH_ID_I2C4, -1, 8, -1},
74 {PERIPH_ID_I2C5, -1, 8, -1},
75 {PERIPH_ID_I2C6, -1, 8, -1},
76 {PERIPH_ID_I2C7, -1, 8, -1},
77 {PERIPH_ID_SPI0, 20, 20, 8},
78 {PERIPH_ID_SPI1, 24, 24, 16},
79 {PERIPH_ID_SPI2, 28, 28, 24},
80 {PERIPH_ID_SDMMC0, 8, 0, -1},
81 {PERIPH_ID_SDMMC1, 12, 10, -1},
82 {PERIPH_ID_SDMMC2, 16, 20, -1},
83 {PERIPH_ID_I2C8, -1, 8, -1},
84 {PERIPH_ID_I2C9, -1, 8, -1},
85 {PERIPH_ID_I2S0, 0, 0, 4},
86 {PERIPH_ID_I2S1, 4, 12, 16},
87 {PERIPH_ID_SPI3, 12, 16, 0},
88 {PERIPH_ID_SPI4, 16, 20, 8},
89 {PERIPH_ID_PWM0, 24, 28, -1},
90 {PERIPH_ID_PWM1, 24, 28, -1},
91 {PERIPH_ID_PWM2, 24, 28, -1},
92 {PERIPH_ID_PWM3, 24, 28, -1},
93 {PERIPH_ID_PWM4, 24, 28, -1},
94 {PERIPH_ID_I2C10, -1, 8, -1},
96 {PERIPH_ID_NONE, -1, -1, -1},
99 /* Epll Clock division values to achive different frequency output */
100 static struct set_epll_con_val exynos5_epll_div[] = {
101 { 192000000, 0, 48, 3, 1, 0 },
102 { 180000000, 0, 45, 3, 1, 0 },
103 { 73728000, 1, 73, 3, 3, 47710 },
104 { 67737600, 1, 90, 4, 3, 20762 },
105 { 49152000, 0, 49, 3, 3, 9961 },
106 { 45158400, 0, 45, 3, 3, 10381 },
107 { 180633600, 0, 45, 3, 1, 10381 }
110 /* exynos: return pll clock frequency */
111 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
113 unsigned long m, p, s = 0, mask, fout;
117 * APLL_CON: MIDV [25:16]
118 * MPLL_CON: MIDV [25:16]
119 * EPLL_CON: MIDV [24:16]
120 * VPLL_CON: MIDV [24:16]
121 * BPLL_CON: MIDV [25:16]: Exynos5
123 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
129 m = (r >> 16) & mask;
136 freq = CONFIG_SYS_CLK_FREQ;
138 if (pllreg == EPLL || pllreg == RPLL) {
140 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
141 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
142 } else if (pllreg == VPLL) {
147 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
150 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
153 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
155 if (proid_is_exynos4210())
157 else if (proid_is_exynos4412())
159 else if (proid_is_exynos5250() || proid_is_exynos5420()
160 || proid_is_exynos5800())
165 fout = (m + k / div) * (freq / (p * (1 << s)));
168 * Exynos4412 / Exynos5250
169 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
172 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
174 if (proid_is_exynos4210())
175 fout = m * (freq / (p * (1 << (s - 1))));
177 fout = m * (freq / (p * (1 << s)));
182 /* exynos4: return pll clock frequency */
183 static unsigned long exynos4_get_pll_clk(int pllreg)
185 struct exynos4_clock *clk =
186 (struct exynos4_clock *)samsung_get_base_clock();
187 unsigned long r, k = 0;
191 r = readl(&clk->apll_con0);
194 r = readl(&clk->mpll_con0);
197 r = readl(&clk->epll_con0);
198 k = readl(&clk->epll_con1);
201 r = readl(&clk->vpll_con0);
202 k = readl(&clk->vpll_con1);
205 printf("Unsupported PLL (%d)\n", pllreg);
209 return exynos_get_pll_clk(pllreg, r, k);
212 /* exynos4x12: return pll clock frequency */
213 static unsigned long exynos4x12_get_pll_clk(int pllreg)
215 struct exynos4x12_clock *clk =
216 (struct exynos4x12_clock *)samsung_get_base_clock();
217 unsigned long r, k = 0;
221 r = readl(&clk->apll_con0);
224 r = readl(&clk->mpll_con0);
227 r = readl(&clk->epll_con0);
228 k = readl(&clk->epll_con1);
231 r = readl(&clk->vpll_con0);
232 k = readl(&clk->vpll_con1);
235 printf("Unsupported PLL (%d)\n", pllreg);
239 return exynos_get_pll_clk(pllreg, r, k);
242 /* exynos5: return pll clock frequency */
243 static unsigned long exynos5_get_pll_clk(int pllreg)
245 struct exynos5_clock *clk =
246 (struct exynos5_clock *)samsung_get_base_clock();
247 unsigned long r, k = 0, fout;
248 unsigned int pll_div2_sel, fout_sel;
252 r = readl(&clk->apll_con0);
255 r = readl(&clk->mpll_con0);
258 r = readl(&clk->epll_con0);
259 k = readl(&clk->epll_con1);
262 r = readl(&clk->vpll_con0);
263 k = readl(&clk->vpll_con1);
266 r = readl(&clk->bpll_con0);
269 printf("Unsupported PLL (%d)\n", pllreg);
273 fout = exynos_get_pll_clk(pllreg, r, k);
275 /* According to the user manual, in EVT1 MPLL and BPLL always gives
276 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
277 if (pllreg == MPLL || pllreg == BPLL) {
278 pll_div2_sel = readl(&clk->pll_div2_sel);
282 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
283 & MPLL_FOUT_SEL_MASK;
286 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
287 & BPLL_FOUT_SEL_MASK;
301 /* exynos542x: return pll clock frequency */
302 static unsigned long exynos542x_get_pll_clk(int pllreg)
304 struct exynos5420_clock *clk =
305 (struct exynos5420_clock *)samsung_get_base_clock();
306 unsigned long r, k = 0;
310 r = readl(&clk->apll_con0);
313 r = readl(&clk->mpll_con0);
316 r = readl(&clk->epll_con0);
317 k = readl(&clk->epll_con1);
320 r = readl(&clk->vpll_con0);
321 k = readl(&clk->vpll_con1);
324 r = readl(&clk->bpll_con0);
327 r = readl(&clk->rpll_con0);
328 k = readl(&clk->rpll_con1);
331 r = readl(&clk->spll_con0);
334 printf("Unsupported PLL (%d)\n", pllreg);
338 return exynos_get_pll_clk(pllreg, r, k);
341 static struct clk_bit_info *get_clk_bit_info(int peripheral)
344 struct clk_bit_info *info;
346 if (proid_is_exynos5420() || proid_is_exynos5800())
347 info = exynos542x_bit_info;
349 info = exynos5_bit_info;
351 for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
352 if (info[i].id == peripheral)
356 if (info[i].id == PERIPH_ID_NONE)
357 debug("ERROR: Peripheral ID %d not found\n", peripheral);
362 static unsigned long exynos5_get_periph_rate(int peripheral)
364 struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
365 unsigned long sclk, sub_clk;
366 unsigned int src, div, sub_div;
367 struct exynos5_clock *clk =
368 (struct exynos5_clock *)samsung_get_base_clock();
370 switch (peripheral) {
371 case PERIPH_ID_UART0:
372 case PERIPH_ID_UART1:
373 case PERIPH_ID_UART2:
374 case PERIPH_ID_UART3:
375 src = readl(&clk->src_peric0);
376 div = readl(&clk->div_peric0);
383 src = readl(&clk->src_peric0);
384 div = readl(&clk->div_peric3);
387 src = readl(&clk->src_mau);
388 div = readl(&clk->div_mau);
391 src = readl(&clk->src_peric1);
392 div = readl(&clk->div_peric1);
395 src = readl(&clk->src_peric1);
396 div = readl(&clk->div_peric2);
400 src = readl(&clk->sclk_src_isp);
401 div = readl(&clk->sclk_div_isp);
403 case PERIPH_ID_SDMMC0:
404 case PERIPH_ID_SDMMC1:
405 case PERIPH_ID_SDMMC2:
406 case PERIPH_ID_SDMMC3:
407 src = readl(&clk->src_fsys);
408 div = readl(&clk->div_fsys1);
418 sclk = exynos5_get_pll_clk(MPLL);
419 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
421 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
423 return (sclk / sub_div) / div;
425 debug("%s: invalid peripheral %d", __func__, peripheral);
429 src = (src >> bit_info->src_bit) & 0xf;
432 case EXYNOS_SRC_MPLL:
433 sclk = exynos5_get_pll_clk(MPLL);
435 case EXYNOS_SRC_EPLL:
436 sclk = exynos5_get_pll_clk(EPLL);
438 case EXYNOS_SRC_VPLL:
439 sclk = exynos5_get_pll_clk(VPLL);
445 /* Ratio clock division for this peripheral */
446 sub_div = (div >> bit_info->div_bit) & 0xf;
447 sub_clk = sclk / (sub_div + 1);
449 /* Pre-ratio clock division for SDMMC0 and 2 */
450 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
451 div = (div >> bit_info->prediv_bit) & 0xff;
452 return sub_clk / (div + 1);
458 static unsigned long exynos542x_get_periph_rate(int peripheral)
460 struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
461 unsigned long sclk, sub_clk = 0;
462 unsigned int src, div, sub_div = 0;
463 struct exynos5420_clock *clk =
464 (struct exynos5420_clock *)samsung_get_base_clock();
466 switch (peripheral) {
467 case PERIPH_ID_UART0:
468 case PERIPH_ID_UART1:
469 case PERIPH_ID_UART2:
470 case PERIPH_ID_UART3:
476 src = readl(&clk->src_peric0);
477 div = readl(&clk->div_peric0);
482 src = readl(&clk->src_peric1);
483 div = readl(&clk->div_peric1);
484 sub_div = readl(&clk->div_peric4);
488 src = readl(&clk->src_isp);
489 div = readl(&clk->div_isp1);
490 sub_div = readl(&clk->div_isp1);
492 case PERIPH_ID_SDMMC0:
493 case PERIPH_ID_SDMMC1:
494 case PERIPH_ID_SDMMC2:
495 case PERIPH_ID_SDMMC3:
496 src = readl(&clk->src_fsys);
497 div = readl(&clk->div_fsys1);
509 case PERIPH_ID_I2C10:
510 sclk = exynos542x_get_pll_clk(MPLL);
511 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
513 return sclk / sub_div;
515 debug("%s: invalid peripheral %d", __func__, peripheral);
519 if (bit_info->src_bit >= 0)
520 src = (src >> bit_info->src_bit) & 0xf;
523 case EXYNOS542X_SRC_MPLL:
524 sclk = exynos542x_get_pll_clk(MPLL);
526 case EXYNOS542X_SRC_SPLL:
527 sclk = exynos542x_get_pll_clk(SPLL);
529 case EXYNOS542X_SRC_EPLL:
530 sclk = exynos542x_get_pll_clk(EPLL);
532 case EXYNOS542X_SRC_RPLL:
533 sclk = exynos542x_get_pll_clk(RPLL);
539 /* Ratio clock division for this peripheral */
540 if (bit_info->div_bit >= 0) {
541 div = (div >> bit_info->div_bit) & 0xf;
542 sub_clk = sclk / (div + 1);
545 if (bit_info->prediv_bit >= 0) {
546 sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
547 return sub_clk / (sub_div + 1);
553 unsigned long clock_get_periph_rate(int peripheral)
555 if (cpu_is_exynos5()) {
556 if (proid_is_exynos5420() || proid_is_exynos5800())
557 return exynos542x_get_periph_rate(peripheral);
558 return exynos5_get_periph_rate(peripheral);
564 /* exynos4: return ARM clock frequency */
565 static unsigned long exynos4_get_arm_clk(void)
567 struct exynos4_clock *clk =
568 (struct exynos4_clock *)samsung_get_base_clock();
570 unsigned long armclk;
571 unsigned int core_ratio;
572 unsigned int core2_ratio;
574 div = readl(&clk->div_cpu0);
576 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
577 core_ratio = (div >> 0) & 0x7;
578 core2_ratio = (div >> 28) & 0x7;
580 armclk = get_pll_clk(APLL) / (core_ratio + 1);
581 armclk /= (core2_ratio + 1);
586 /* exynos4x12: return ARM clock frequency */
587 static unsigned long exynos4x12_get_arm_clk(void)
589 struct exynos4x12_clock *clk =
590 (struct exynos4x12_clock *)samsung_get_base_clock();
592 unsigned long armclk;
593 unsigned int core_ratio;
594 unsigned int core2_ratio;
596 div = readl(&clk->div_cpu0);
598 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
599 core_ratio = (div >> 0) & 0x7;
600 core2_ratio = (div >> 28) & 0x7;
602 armclk = get_pll_clk(APLL) / (core_ratio + 1);
603 armclk /= (core2_ratio + 1);
608 /* exynos5: return ARM clock frequency */
609 static unsigned long exynos5_get_arm_clk(void)
611 struct exynos5_clock *clk =
612 (struct exynos5_clock *)samsung_get_base_clock();
614 unsigned long armclk;
615 unsigned int arm_ratio;
616 unsigned int arm2_ratio;
618 div = readl(&clk->div_cpu0);
620 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
621 arm_ratio = (div >> 0) & 0x7;
622 arm2_ratio = (div >> 28) & 0x7;
624 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
625 armclk /= (arm2_ratio + 1);
630 /* exynos4: return pwm clock frequency */
631 static unsigned long exynos4_get_pwm_clk(void)
633 struct exynos4_clock *clk =
634 (struct exynos4_clock *)samsung_get_base_clock();
635 unsigned long pclk, sclk;
639 if (s5p_get_cpu_rev() == 0) {
644 sel = readl(&clk->src_peril0);
645 sel = (sel >> 24) & 0xf;
648 sclk = get_pll_clk(MPLL);
650 sclk = get_pll_clk(EPLL);
652 sclk = get_pll_clk(VPLL);
660 ratio = readl(&clk->div_peril3);
662 } else if (s5p_get_cpu_rev() == 1) {
663 sclk = get_pll_clk(MPLL);
668 pclk = sclk / (ratio + 1);
673 /* exynos4x12: return pwm clock frequency */
674 static unsigned long exynos4x12_get_pwm_clk(void)
676 unsigned long pclk, sclk;
679 sclk = get_pll_clk(MPLL);
682 pclk = sclk / (ratio + 1);
687 /* exynos5420: return pwm clock frequency */
688 static unsigned long exynos5420_get_pwm_clk(void)
690 struct exynos5420_clock *clk =
691 (struct exynos5420_clock *)samsung_get_base_clock();
692 unsigned long pclk, sclk;
699 ratio = readl(&clk->div_peric0);
700 ratio = (ratio >> 28) & 0xf;
701 sclk = get_pll_clk(MPLL);
703 pclk = sclk / (ratio + 1);
708 /* exynos4: return uart clock frequency */
709 static unsigned long exynos4_get_uart_clk(int dev_index)
711 struct exynos4_clock *clk =
712 (struct exynos4_clock *)samsung_get_base_clock();
713 unsigned long uclk, sclk;
726 sel = readl(&clk->src_peril0);
727 sel = (sel >> (dev_index << 2)) & 0xf;
730 sclk = get_pll_clk(MPLL);
732 sclk = get_pll_clk(EPLL);
734 sclk = get_pll_clk(VPLL);
743 * UART3_RATIO [12:15]
744 * UART4_RATIO [16:19]
745 * UART5_RATIO [23:20]
747 ratio = readl(&clk->div_peril0);
748 ratio = (ratio >> (dev_index << 2)) & 0xf;
750 uclk = sclk / (ratio + 1);
755 /* exynos4x12: return uart clock frequency */
756 static unsigned long exynos4x12_get_uart_clk(int dev_index)
758 struct exynos4x12_clock *clk =
759 (struct exynos4x12_clock *)samsung_get_base_clock();
760 unsigned long uclk, sclk;
772 sel = readl(&clk->src_peril0);
773 sel = (sel >> (dev_index << 2)) & 0xf;
776 sclk = get_pll_clk(MPLL);
778 sclk = get_pll_clk(EPLL);
780 sclk = get_pll_clk(VPLL);
789 * UART3_RATIO [12:15]
790 * UART4_RATIO [16:19]
792 ratio = readl(&clk->div_peril0);
793 ratio = (ratio >> (dev_index << 2)) & 0xf;
795 uclk = sclk / (ratio + 1);
800 /* exynos5: return uart clock frequency */
801 static unsigned long exynos5_get_uart_clk(int dev_index)
803 struct exynos5_clock *clk =
804 (struct exynos5_clock *)samsung_get_base_clock();
805 unsigned long uclk, sclk;
818 sel = readl(&clk->src_peric0);
819 sel = (sel >> (dev_index << 2)) & 0xf;
822 sclk = get_pll_clk(MPLL);
824 sclk = get_pll_clk(EPLL);
826 sclk = get_pll_clk(VPLL);
835 * UART3_RATIO [12:15]
836 * UART4_RATIO [16:19]
837 * UART5_RATIO [23:20]
839 ratio = readl(&clk->div_peric0);
840 ratio = (ratio >> (dev_index << 2)) & 0xf;
842 uclk = sclk / (ratio + 1);
847 /* exynos5420: return uart clock frequency */
848 static unsigned long exynos5420_get_uart_clk(int dev_index)
850 struct exynos5420_clock *clk =
851 (struct exynos5420_clock *)samsung_get_base_clock();
852 unsigned long uclk, sclk;
862 * generalised calculation as follows
863 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
865 sel = readl(&clk->src_peric0);
866 sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
869 sclk = get_pll_clk(MPLL);
871 sclk = get_pll_clk(EPLL);
873 sclk = get_pll_clk(RPLL);
880 * UART1_RATIO [15:12]
881 * UART2_RATIO [19:16]
882 * UART3_RATIO [23:20]
883 * generalised calculation as follows
884 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
886 ratio = readl(&clk->div_peric0);
887 ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
889 uclk = sclk / (ratio + 1);
894 static unsigned long exynos4_get_mmc_clk(int dev_index)
896 struct exynos4_clock *clk =
897 (struct exynos4_clock *)samsung_get_base_clock();
898 unsigned long uclk, sclk;
899 unsigned int sel, ratio, pre_ratio;
902 sel = readl(&clk->src_fsys);
903 sel = (sel >> (dev_index << 2)) & 0xf;
906 sclk = get_pll_clk(MPLL);
908 sclk = get_pll_clk(EPLL);
910 sclk = get_pll_clk(VPLL);
917 ratio = readl(&clk->div_fsys1);
918 pre_ratio = readl(&clk->div_fsys1);
922 ratio = readl(&clk->div_fsys2);
923 pre_ratio = readl(&clk->div_fsys2);
926 ratio = readl(&clk->div_fsys3);
927 pre_ratio = readl(&clk->div_fsys3);
933 if (dev_index == 1 || dev_index == 3)
936 ratio = (ratio >> shift) & 0xf;
937 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
938 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
943 static unsigned long exynos5_get_mmc_clk(int dev_index)
945 struct exynos5_clock *clk =
946 (struct exynos5_clock *)samsung_get_base_clock();
947 unsigned long uclk, sclk;
948 unsigned int sel, ratio, pre_ratio;
951 sel = readl(&clk->src_fsys);
952 sel = (sel >> (dev_index << 2)) & 0xf;
955 sclk = get_pll_clk(MPLL);
957 sclk = get_pll_clk(EPLL);
959 sclk = get_pll_clk(VPLL);
966 ratio = readl(&clk->div_fsys1);
967 pre_ratio = readl(&clk->div_fsys1);
971 ratio = readl(&clk->div_fsys2);
972 pre_ratio = readl(&clk->div_fsys2);
978 if (dev_index == 1 || dev_index == 3)
981 ratio = (ratio >> shift) & 0xf;
982 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
983 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
988 static unsigned long exynos5420_get_mmc_clk(int dev_index)
990 struct exynos5420_clock *clk =
991 (struct exynos5420_clock *)samsung_get_base_clock();
992 unsigned long uclk, sclk;
993 unsigned int sel, ratio;
1000 * generalised calculation as follows
1001 * sel = (sel >> ((dev_index * 4) + 8)) & mask
1003 sel = readl(&clk->src_fsys);
1004 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
1007 sclk = get_pll_clk(MPLL);
1008 else if (sel == 0x4)
1009 sclk = get_pll_clk(SPLL);
1010 else if (sel == 0x6)
1011 sclk = get_pll_clk(EPLL);
1018 * MMC1_RATIO [19:10]
1019 * MMC2_RATIO [29:20]
1020 * generalised calculation as follows
1021 * ratio = (ratio >> (dev_index * 10)) & mask
1023 ratio = readl(&clk->div_fsys1);
1024 ratio = (ratio >> (dev_index * 10)) & 0x3ff;
1026 uclk = (sclk / (ratio + 1));
1031 /* exynos4: set the mmc clock */
1032 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
1034 struct exynos4_clock *clk =
1035 (struct exynos4_clock *)samsung_get_base_clock();
1036 unsigned int addr, clear_bit, set_bit;
1040 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
1042 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
1046 if (dev_index < 2) {
1047 addr = (unsigned int)&clk->div_fsys1;
1048 clear_bit = MASK_PRE_RATIO(dev_index);
1049 set_bit = SET_PRE_RATIO(dev_index, div);
1050 } else if (dev_index == 4) {
1051 addr = (unsigned int)&clk->div_fsys3;
1053 /* MMC4 is controlled with the MMC4_RATIO value */
1054 clear_bit = MASK_RATIO(dev_index);
1055 set_bit = SET_RATIO(dev_index, div);
1057 addr = (unsigned int)&clk->div_fsys2;
1059 clear_bit = MASK_PRE_RATIO(dev_index);
1060 set_bit = SET_PRE_RATIO(dev_index, div);
1063 clrsetbits_le32(addr, clear_bit, set_bit);
1066 /* exynos5: set the mmc clock */
1067 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
1069 struct exynos5_clock *clk =
1070 (struct exynos5_clock *)samsung_get_base_clock();
1075 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
1077 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
1079 if (dev_index < 2) {
1080 addr = (unsigned int)&clk->div_fsys1;
1082 addr = (unsigned int)&clk->div_fsys2;
1086 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
1087 (div & 0xff) << ((dev_index << 4) + 8));
1090 /* exynos5: set the mmc clock */
1091 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
1093 struct exynos5420_clock *clk =
1094 (struct exynos5420_clock *)samsung_get_base_clock();
1101 * MMC1_RATIO [19:10]
1102 * MMC2_RATIO [29:20]
1104 addr = (unsigned int)&clk->div_fsys1;
1105 shift = dev_index * 10;
1107 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
1110 /* get_lcd_clk: return lcd clock frequency */
1111 static unsigned long exynos4_get_lcd_clk(void)
1113 struct exynos4_clock *clk =
1114 (struct exynos4_clock *)samsung_get_base_clock();
1115 unsigned long pclk, sclk;
1123 sel = readl(&clk->src_lcd0);
1132 sclk = get_pll_clk(MPLL);
1133 else if (sel == 0x7)
1134 sclk = get_pll_clk(EPLL);
1135 else if (sel == 0x8)
1136 sclk = get_pll_clk(VPLL);
1144 ratio = readl(&clk->div_lcd0);
1145 ratio = ratio & 0xf;
1147 pclk = sclk / (ratio + 1);
1152 /* get_lcd_clk: return lcd clock frequency */
1153 static unsigned long exynos5_get_lcd_clk(void)
1155 struct exynos5_clock *clk =
1156 (struct exynos5_clock *)samsung_get_base_clock();
1157 unsigned long pclk, sclk;
1165 sel = readl(&clk->src_disp1_0);
1174 sclk = get_pll_clk(MPLL);
1175 else if (sel == 0x7)
1176 sclk = get_pll_clk(EPLL);
1177 else if (sel == 0x8)
1178 sclk = get_pll_clk(VPLL);
1186 ratio = readl(&clk->div_disp1_0);
1187 ratio = ratio & 0xf;
1189 pclk = sclk / (ratio + 1);
1194 static unsigned long exynos5420_get_lcd_clk(void)
1196 struct exynos5420_clock *clk =
1197 (struct exynos5420_clock *)samsung_get_base_clock();
1198 unsigned long pclk, sclk;
1208 sel = readl(&clk->src_disp10);
1212 sclk = get_pll_clk(SPLL);
1214 sclk = get_pll_clk(RPLL);
1220 ratio = readl(&clk->div_disp10);
1221 ratio = ratio & 0xf;
1223 pclk = sclk / (ratio + 1);
1228 void exynos4_set_lcd_clk(void)
1230 struct exynos4_clock *clk =
1231 (struct exynos4_clock *)samsung_get_base_clock();
1243 setbits_le32(&clk->gate_block, 1 << 4);
1249 * MDNIE_PWM0_SEL [8:11]
1251 * set lcd0 src clock 0x6: SCLK_MPLL
1253 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
1263 * Gating all clocks for FIMD0
1265 setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
1270 * MDNIE0_RATIO [7:4]
1271 * MDNIE_PWM0_RATIO [11:8]
1272 * MDNIE_PWM_PRE_RATIO [15:12]
1273 * MIPI0_RATIO [19:16]
1274 * MIPI0_PRE_RATIO [23:20]
1277 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
1280 void exynos5_set_lcd_clk(void)
1282 struct exynos5_clock *clk =
1283 (struct exynos5_clock *)samsung_get_base_clock();
1295 setbits_le32(&clk->gate_block, 1 << 4);
1301 * MDNIE_PWM0_SEL [8:11]
1303 * set lcd0 src clock 0x6: SCLK_MPLL
1305 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
1315 * Gating all clocks for FIMD0
1317 setbits_le32(&clk->gate_ip_disp1, 1 << 0);
1322 * MDNIE0_RATIO [7:4]
1323 * MDNIE_PWM0_RATIO [11:8]
1324 * MDNIE_PWM_PRE_RATIO [15:12]
1325 * MIPI0_RATIO [19:16]
1326 * MIPI0_PRE_RATIO [23:20]
1329 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1332 void exynos5420_set_lcd_clk(void)
1334 struct exynos5420_clock *clk =
1335 (struct exynos5420_clock *)samsung_get_base_clock();
1344 cfg = readl(&clk->src_disp10);
1347 writel(cfg, &clk->src_disp10);
1353 cfg = readl(&clk->div_disp10);
1356 writel(cfg, &clk->div_disp10);
1359 void exynos4_set_mipi_clk(void)
1361 struct exynos4_clock *clk =
1362 (struct exynos4_clock *)samsung_get_base_clock();
1368 * MDNIE_PWM0_SEL [8:11]
1370 * set mipi0 src clock 0x6: SCLK_MPLL
1372 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
1378 * MDNIE_PWM0_MASK [8]
1380 * set src mask mipi0 0x1: Unmask
1382 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
1392 * Gating all clocks for MIPI0
1394 setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
1399 * MDNIE0_RATIO [7:4]
1400 * MDNIE_PWM0_RATIO [11:8]
1401 * MDNIE_PWM_PRE_RATIO [15:12]
1402 * MIPI0_RATIO [19:16]
1403 * MIPI0_PRE_RATIO [23:20]
1406 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
1412 * exynos5: obtaining the I2C clock
1414 static unsigned long exynos5_get_i2c_clk(void)
1416 struct exynos5_clock *clk =
1417 (struct exynos5_clock *)samsung_get_base_clock();
1418 unsigned long aclk_66, aclk_66_pre, sclk;
1421 sclk = get_pll_clk(MPLL);
1423 ratio = (readl(&clk->div_top1)) >> 24;
1425 aclk_66_pre = sclk / (ratio + 1);
1426 ratio = readl(&clk->div_top0);
1428 aclk_66 = aclk_66_pre / (ratio + 1);
1432 int exynos5_set_epll_clk(unsigned long rate)
1434 unsigned int epll_con, epll_con_k;
1436 unsigned int lockcnt;
1438 struct exynos5_clock *clk =
1439 (struct exynos5_clock *)samsung_get_base_clock();
1441 epll_con = readl(&clk->epll_con0);
1442 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1443 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1444 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1445 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1446 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1448 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1449 if (exynos5_epll_div[i].freq_out == rate)
1453 if (i == ARRAY_SIZE(exynos5_epll_div))
1456 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1457 epll_con |= exynos5_epll_div[i].en_lock_det <<
1458 EPLL_CON0_LOCK_DET_EN_SHIFT;
1459 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1460 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1461 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1464 * Required period ( in cycles) to genarate a stable clock output.
1465 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1466 * frequency input (as per spec)
1468 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1470 writel(lockcnt, &clk->epll_lock);
1471 writel(epll_con, &clk->epll_con0);
1472 writel(epll_con_k, &clk->epll_con1);
1474 start = get_timer(0);
1476 while (!(readl(&clk->epll_con0) &
1477 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1478 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1479 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1486 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1488 struct exynos5_clock *clk =
1489 (struct exynos5_clock *)samsung_get_base_clock();
1490 unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1493 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1494 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1495 (CLK_SRC_SCLK_EPLL));
1496 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1497 } else if (i2s_id == 1) {
1498 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1499 (CLK_SRC_SCLK_EPLL));
1506 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1507 unsigned int dst_frq,
1508 unsigned int i2s_id)
1510 struct exynos5_clock *clk =
1511 (struct exynos5_clock *)samsung_get_base_clock();
1514 if ((dst_frq == 0) || (src_frq == 0)) {
1515 debug("%s: Invalid requency input for prescaler\n", __func__);
1516 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1520 div = (src_frq / dst_frq);
1522 if (div > AUDIO_0_RATIO_MASK) {
1523 debug("%s: Frequency ratio is out of range\n",
1525 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1528 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1529 (div & AUDIO_0_RATIO_MASK));
1530 } else if(i2s_id == 1) {
1531 if (div > AUDIO_1_RATIO_MASK) {
1532 debug("%s: Frequency ratio is out of range\n",
1534 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1537 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1538 (div & AUDIO_1_RATIO_MASK));
1546 * Linearly searches for the most accurate main and fine stage clock scalars
1547 * (divisors) for a specified target frequency and scalar bit sizes by checking
1548 * all multiples of main_scalar_bits values. Will always return scalars up to or
1549 * slower than target.
1551 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1552 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1553 * @param input_freq Clock frequency to be scaled in Hz
1554 * @param target_freq Desired clock frequency in Hz
1555 * @param best_fine_scalar Pointer to store the fine stage divisor
1557 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1560 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1561 unsigned int fine_scalar_bits, unsigned int input_rate,
1562 unsigned int target_rate, unsigned int *best_fine_scalar)
1565 int best_main_scalar = -1;
1566 unsigned int best_error = target_rate;
1567 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1568 const unsigned int loops = 1 << main_scaler_bits;
1570 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1573 assert(best_fine_scalar != NULL);
1574 assert(main_scaler_bits <= fine_scalar_bits);
1576 *best_fine_scalar = 1;
1578 if (input_rate == 0 || target_rate == 0)
1581 if (target_rate >= input_rate)
1584 for (i = 1; i <= loops; i++) {
1585 const unsigned int effective_div =
1586 max(min(input_rate / i / target_rate, cap), 1U);
1587 const unsigned int effective_rate = input_rate / i /
1589 const int error = target_rate - effective_rate;
1591 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1592 effective_rate, error);
1594 if (error >= 0 && error <= best_error) {
1596 best_main_scalar = i;
1597 *best_fine_scalar = effective_div;
1601 return best_main_scalar;
1604 static int exynos5_set_spi_clk(enum periph_id periph_id,
1607 struct exynos5_clock *clk =
1608 (struct exynos5_clock *)samsung_get_base_clock();
1611 unsigned shift, pre_shift;
1612 unsigned mask = 0xff;
1615 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1617 debug("%s: Cannot set clock rate for periph %d",
1618 __func__, periph_id);
1624 switch (periph_id) {
1625 case PERIPH_ID_SPI0:
1626 reg = &clk->div_peric1;
1630 case PERIPH_ID_SPI1:
1631 reg = &clk->div_peric1;
1635 case PERIPH_ID_SPI2:
1636 reg = &clk->div_peric2;
1640 case PERIPH_ID_SPI3:
1641 reg = &clk->sclk_div_isp;
1645 case PERIPH_ID_SPI4:
1646 reg = &clk->sclk_div_isp;
1651 debug("%s: Unsupported peripheral ID %d\n", __func__,
1655 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1656 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1661 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1664 struct exynos5420_clock *clk =
1665 (struct exynos5420_clock *)samsung_get_base_clock();
1668 unsigned shift, pre_shift;
1669 unsigned div_mask = 0xf, pre_div_mask = 0xff;
1673 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1675 debug("%s: Cannot set clock rate for periph %d",
1676 __func__, periph_id);
1682 switch (periph_id) {
1683 case PERIPH_ID_SPI0:
1684 reg = &clk->div_peric1;
1686 pre_reg = &clk->div_peric4;
1689 case PERIPH_ID_SPI1:
1690 reg = &clk->div_peric1;
1692 pre_reg = &clk->div_peric4;
1695 case PERIPH_ID_SPI2:
1696 reg = &clk->div_peric1;
1698 pre_reg = &clk->div_peric4;
1701 case PERIPH_ID_SPI3:
1702 reg = &clk->div_isp1;
1704 pre_reg = &clk->div_isp1;
1707 case PERIPH_ID_SPI4:
1708 reg = &clk->div_isp1;
1710 pre_reg = &clk->div_isp1;
1714 debug("%s: Unsupported peripheral ID %d\n", __func__,
1719 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1720 clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1721 (fine & pre_div_mask) << pre_shift);
1726 static unsigned long exynos4_get_i2c_clk(void)
1728 struct exynos4_clock *clk =
1729 (struct exynos4_clock *)samsung_get_base_clock();
1730 unsigned long sclk, aclk_100;
1733 sclk = get_pll_clk(APLL);
1735 ratio = (readl(&clk->div_top)) >> 4;
1737 aclk_100 = sclk / (ratio + 1);
1741 unsigned long get_pll_clk(int pllreg)
1743 if (cpu_is_exynos5()) {
1744 if (proid_is_exynos5420() || proid_is_exynos5800())
1745 return exynos542x_get_pll_clk(pllreg);
1746 return exynos5_get_pll_clk(pllreg);
1748 if (proid_is_exynos4412())
1749 return exynos4x12_get_pll_clk(pllreg);
1750 return exynos4_get_pll_clk(pllreg);
1754 unsigned long get_arm_clk(void)
1756 if (cpu_is_exynos5())
1757 return exynos5_get_arm_clk();
1759 if (proid_is_exynos4412())
1760 return exynos4x12_get_arm_clk();
1761 return exynos4_get_arm_clk();
1765 unsigned long get_i2c_clk(void)
1767 if (cpu_is_exynos5()) {
1768 return exynos5_get_i2c_clk();
1769 } else if (cpu_is_exynos4()) {
1770 return exynos4_get_i2c_clk();
1772 debug("I2C clock is not set for this CPU\n");
1777 unsigned long get_pwm_clk(void)
1779 if (cpu_is_exynos5()) {
1780 if (proid_is_exynos5420() || proid_is_exynos5800())
1781 return exynos5420_get_pwm_clk();
1782 return clock_get_periph_rate(PERIPH_ID_PWM0);
1784 if (proid_is_exynos4412())
1785 return exynos4x12_get_pwm_clk();
1786 return exynos4_get_pwm_clk();
1790 unsigned long get_uart_clk(int dev_index)
1792 if (cpu_is_exynos5()) {
1793 if (proid_is_exynos5420() || proid_is_exynos5800())
1794 return exynos5420_get_uart_clk(dev_index);
1795 return exynos5_get_uart_clk(dev_index);
1797 if (proid_is_exynos4412())
1798 return exynos4x12_get_uart_clk(dev_index);
1799 return exynos4_get_uart_clk(dev_index);
1803 unsigned long get_mmc_clk(int dev_index)
1805 if (cpu_is_exynos5()) {
1806 if (proid_is_exynos5420() || proid_is_exynos5800())
1807 return exynos5420_get_mmc_clk(dev_index);
1808 return exynos5_get_mmc_clk(dev_index);
1810 return exynos4_get_mmc_clk(dev_index);
1814 void set_mmc_clk(int dev_index, unsigned int div)
1816 /* If want to set correct value, it needs to substract one from div.*/
1820 if (cpu_is_exynos5()) {
1821 if (proid_is_exynos5420() || proid_is_exynos5800())
1822 exynos5420_set_mmc_clk(dev_index, div);
1824 exynos5_set_mmc_clk(dev_index, div);
1826 exynos4_set_mmc_clk(dev_index, div);
1830 unsigned long get_lcd_clk(void)
1832 if (cpu_is_exynos4())
1833 return exynos4_get_lcd_clk();
1835 if (proid_is_exynos5420() || proid_is_exynos5800())
1836 return exynos5420_get_lcd_clk();
1838 return exynos5_get_lcd_clk();
1842 void set_lcd_clk(void)
1844 if (cpu_is_exynos4())
1845 exynos4_set_lcd_clk();
1847 if (proid_is_exynos5250())
1848 exynos5_set_lcd_clk();
1849 else if (proid_is_exynos5420() || proid_is_exynos5800())
1850 exynos5420_set_lcd_clk();
1854 void set_mipi_clk(void)
1856 if (cpu_is_exynos4())
1857 exynos4_set_mipi_clk();
1860 int set_spi_clk(int periph_id, unsigned int rate)
1862 if (cpu_is_exynos5()) {
1863 if (proid_is_exynos5420() || proid_is_exynos5800())
1864 return exynos5420_set_spi_clk(periph_id, rate);
1865 return exynos5_set_spi_clk(periph_id, rate);
1871 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1872 unsigned int i2s_id)
1874 if (cpu_is_exynos5())
1875 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1880 int set_i2s_clk_source(unsigned int i2s_id)
1882 if (cpu_is_exynos5())
1883 return exynos5_set_i2s_clk_source(i2s_id);
1888 int set_epll_clk(unsigned long rate)
1890 if (cpu_is_exynos5())
1891 return exynos5_set_epll_clk(rate);