2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/periph.h>
14 #define PLL_DIV_1024 1024
15 #define PLL_DIV_65535 65535
16 #define PLL_DIV_65536 65536
19 * This structure is to store the src bit, div bit and prediv bit
20 * positions of the peripheral clocks of the src and div registers
29 /* periph_id src_bit div_bit prediv_bit */
30 static struct clk_bit_info clk_bit_info[] = {
31 {PERIPH_ID_UART0, 0, 0, -1},
32 {PERIPH_ID_UART1, 4, 4, -1},
33 {PERIPH_ID_UART2, 8, 8, -1},
34 {PERIPH_ID_UART3, 12, 12, -1},
35 {PERIPH_ID_I2C0, -1, 24, 0},
36 {PERIPH_ID_I2C1, -1, 24, 0},
37 {PERIPH_ID_I2C2, -1, 24, 0},
38 {PERIPH_ID_I2C3, -1, 24, 0},
39 {PERIPH_ID_I2C4, -1, 24, 0},
40 {PERIPH_ID_I2C5, -1, 24, 0},
41 {PERIPH_ID_I2C6, -1, 24, 0},
42 {PERIPH_ID_I2C7, -1, 24, 0},
43 {PERIPH_ID_SPI0, 16, 0, 8},
44 {PERIPH_ID_SPI1, 20, 16, 24},
45 {PERIPH_ID_SPI2, 24, 0, 8},
46 {PERIPH_ID_SDMMC0, 0, 0, 8},
47 {PERIPH_ID_SDMMC1, 4, 16, 24},
48 {PERIPH_ID_SDMMC2, 8, 0, 8},
49 {PERIPH_ID_SDMMC3, 12, 16, 24},
50 {PERIPH_ID_I2S0, 0, 0, 4},
51 {PERIPH_ID_I2S1, 4, 12, 16},
52 {PERIPH_ID_SPI3, 0, 0, 4},
53 {PERIPH_ID_SPI4, 4, 12, 16},
54 {PERIPH_ID_SDMMC4, 16, 0, 8},
55 {PERIPH_ID_PWM0, 24, 0, -1},
56 {PERIPH_ID_PWM1, 24, 0, -1},
57 {PERIPH_ID_PWM2, 24, 0, -1},
58 {PERIPH_ID_PWM3, 24, 0, -1},
59 {PERIPH_ID_PWM4, 24, 0, -1},
61 {PERIPH_ID_NONE, -1, -1, -1},
64 /* Epll Clock division values to achive different frequency output */
65 static struct set_epll_con_val exynos5_epll_div[] = {
66 { 192000000, 0, 48, 3, 1, 0 },
67 { 180000000, 0, 45, 3, 1, 0 },
68 { 73728000, 1, 73, 3, 3, 47710 },
69 { 67737600, 1, 90, 4, 3, 20762 },
70 { 49152000, 0, 49, 3, 3, 9961 },
71 { 45158400, 0, 45, 3, 3, 10381 },
72 { 180633600, 0, 45, 3, 1, 10381 }
75 /* exynos: return pll clock frequency */
76 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
78 unsigned long m, p, s = 0, mask, fout;
82 * APLL_CON: MIDV [25:16]
83 * MPLL_CON: MIDV [25:16]
84 * EPLL_CON: MIDV [24:16]
85 * VPLL_CON: MIDV [24:16]
86 * BPLL_CON: MIDV [25:16]: Exynos5
88 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
101 freq = CONFIG_SYS_CLK_FREQ;
103 if (pllreg == EPLL || pllreg == RPLL) {
105 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
106 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
107 } else if (pllreg == VPLL) {
112 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
115 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
118 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
120 if (proid_is_exynos4210())
122 else if (proid_is_exynos4412())
124 else if (proid_is_exynos5250() || proid_is_exynos5420()
125 || proid_is_exynos5800())
130 fout = (m + k / div) * (freq / (p * (1 << s)));
133 * Exynos4412 / Exynos5250
134 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
137 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
139 if (proid_is_exynos4210())
140 fout = m * (freq / (p * (1 << (s - 1))));
142 fout = m * (freq / (p * (1 << s)));
147 /* exynos4: return pll clock frequency */
148 static unsigned long exynos4_get_pll_clk(int pllreg)
150 struct exynos4_clock *clk =
151 (struct exynos4_clock *)samsung_get_base_clock();
152 unsigned long r, k = 0;
156 r = readl(&clk->apll_con0);
159 r = readl(&clk->mpll_con0);
162 r = readl(&clk->epll_con0);
163 k = readl(&clk->epll_con1);
166 r = readl(&clk->vpll_con0);
167 k = readl(&clk->vpll_con1);
170 printf("Unsupported PLL (%d)\n", pllreg);
174 return exynos_get_pll_clk(pllreg, r, k);
177 /* exynos4x12: return pll clock frequency */
178 static unsigned long exynos4x12_get_pll_clk(int pllreg)
180 struct exynos4x12_clock *clk =
181 (struct exynos4x12_clock *)samsung_get_base_clock();
182 unsigned long r, k = 0;
186 r = readl(&clk->apll_con0);
189 r = readl(&clk->mpll_con0);
192 r = readl(&clk->epll_con0);
193 k = readl(&clk->epll_con1);
196 r = readl(&clk->vpll_con0);
197 k = readl(&clk->vpll_con1);
200 printf("Unsupported PLL (%d)\n", pllreg);
204 return exynos_get_pll_clk(pllreg, r, k);
207 /* exynos5: return pll clock frequency */
208 static unsigned long exynos5_get_pll_clk(int pllreg)
210 struct exynos5_clock *clk =
211 (struct exynos5_clock *)samsung_get_base_clock();
212 unsigned long r, k = 0, fout;
213 unsigned int pll_div2_sel, fout_sel;
217 r = readl(&clk->apll_con0);
220 r = readl(&clk->mpll_con0);
223 r = readl(&clk->epll_con0);
224 k = readl(&clk->epll_con1);
227 r = readl(&clk->vpll_con0);
228 k = readl(&clk->vpll_con1);
231 r = readl(&clk->bpll_con0);
234 printf("Unsupported PLL (%d)\n", pllreg);
238 fout = exynos_get_pll_clk(pllreg, r, k);
240 /* According to the user manual, in EVT1 MPLL and BPLL always gives
241 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
242 if (pllreg == MPLL || pllreg == BPLL) {
243 pll_div2_sel = readl(&clk->pll_div2_sel);
247 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
248 & MPLL_FOUT_SEL_MASK;
251 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
252 & BPLL_FOUT_SEL_MASK;
266 /* exynos542x: return pll clock frequency */
267 static unsigned long exynos542x_get_pll_clk(int pllreg)
269 struct exynos5420_clock *clk =
270 (struct exynos5420_clock *)samsung_get_base_clock();
271 unsigned long r, k = 0;
275 r = readl(&clk->apll_con0);
278 r = readl(&clk->mpll_con0);
281 r = readl(&clk->epll_con0);
282 k = readl(&clk->epll_con1);
285 r = readl(&clk->vpll_con0);
286 k = readl(&clk->vpll_con1);
289 r = readl(&clk->bpll_con0);
292 r = readl(&clk->rpll_con0);
293 k = readl(&clk->rpll_con1);
296 r = readl(&clk->spll_con0);
299 printf("Unsupported PLL (%d)\n", pllreg);
303 return exynos_get_pll_clk(pllreg, r, k);
306 static struct clk_bit_info *get_clk_bit_info(int peripheral)
310 for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
311 if (clk_bit_info[i].id == peripheral)
315 if (clk_bit_info[i].id == PERIPH_ID_NONE)
316 debug("ERROR: Peripheral ID %d not found\n", peripheral);
318 return &clk_bit_info[i];
321 static unsigned long exynos5_get_periph_rate(int peripheral)
323 struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
324 unsigned long sclk, sub_clk;
325 unsigned int src, div, sub_div;
326 struct exynos5_clock *clk =
327 (struct exynos5_clock *)samsung_get_base_clock();
329 switch (peripheral) {
330 case PERIPH_ID_UART0:
331 case PERIPH_ID_UART1:
332 case PERIPH_ID_UART2:
333 case PERIPH_ID_UART3:
334 src = readl(&clk->src_peric0);
335 div = readl(&clk->div_peric0);
342 src = readl(&clk->src_peric0);
343 div = readl(&clk->div_peric3);
346 src = readl(&clk->src_mau);
347 div = readl(&clk->div_mau);
350 src = readl(&clk->src_peric1);
351 div = readl(&clk->div_peric1);
354 src = readl(&clk->src_peric1);
355 div = readl(&clk->div_peric2);
359 src = readl(&clk->sclk_src_isp);
360 div = readl(&clk->sclk_div_isp);
362 case PERIPH_ID_SDMMC0:
363 case PERIPH_ID_SDMMC1:
364 case PERIPH_ID_SDMMC2:
365 case PERIPH_ID_SDMMC3:
366 src = readl(&clk->src_fsys);
367 div = readl(&clk->div_fsys1);
377 sclk = exynos5_get_pll_clk(MPLL);
378 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
380 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
382 return (sclk / sub_div) / div;
384 debug("%s: invalid peripheral %d", __func__, peripheral);
388 src = (src >> bit_info->src_bit) & 0xf;
391 case EXYNOS_SRC_MPLL:
392 sclk = exynos5_get_pll_clk(MPLL);
394 case EXYNOS_SRC_EPLL:
395 sclk = exynos5_get_pll_clk(EPLL);
397 case EXYNOS_SRC_VPLL:
398 sclk = exynos5_get_pll_clk(VPLL);
404 /* Ratio clock division for this peripheral */
405 sub_div = (div >> bit_info->div_bit) & 0xf;
406 sub_clk = sclk / (sub_div + 1);
408 /* Pre-ratio clock division for SDMMC0 and 2 */
409 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
410 div = (div >> bit_info->prediv_bit) & 0xff;
411 return sub_clk / (div + 1);
417 unsigned long clock_get_periph_rate(int peripheral)
419 if (cpu_is_exynos5())
420 return exynos5_get_periph_rate(peripheral);
425 /* exynos4: return ARM clock frequency */
426 static unsigned long exynos4_get_arm_clk(void)
428 struct exynos4_clock *clk =
429 (struct exynos4_clock *)samsung_get_base_clock();
431 unsigned long armclk;
432 unsigned int core_ratio;
433 unsigned int core2_ratio;
435 div = readl(&clk->div_cpu0);
437 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
438 core_ratio = (div >> 0) & 0x7;
439 core2_ratio = (div >> 28) & 0x7;
441 armclk = get_pll_clk(APLL) / (core_ratio + 1);
442 armclk /= (core2_ratio + 1);
447 /* exynos4x12: return ARM clock frequency */
448 static unsigned long exynos4x12_get_arm_clk(void)
450 struct exynos4x12_clock *clk =
451 (struct exynos4x12_clock *)samsung_get_base_clock();
453 unsigned long armclk;
454 unsigned int core_ratio;
455 unsigned int core2_ratio;
457 div = readl(&clk->div_cpu0);
459 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
460 core_ratio = (div >> 0) & 0x7;
461 core2_ratio = (div >> 28) & 0x7;
463 armclk = get_pll_clk(APLL) / (core_ratio + 1);
464 armclk /= (core2_ratio + 1);
469 /* exynos5: return ARM clock frequency */
470 static unsigned long exynos5_get_arm_clk(void)
472 struct exynos5_clock *clk =
473 (struct exynos5_clock *)samsung_get_base_clock();
475 unsigned long armclk;
476 unsigned int arm_ratio;
477 unsigned int arm2_ratio;
479 div = readl(&clk->div_cpu0);
481 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
482 arm_ratio = (div >> 0) & 0x7;
483 arm2_ratio = (div >> 28) & 0x7;
485 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
486 armclk /= (arm2_ratio + 1);
491 /* exynos4: return pwm clock frequency */
492 static unsigned long exynos4_get_pwm_clk(void)
494 struct exynos4_clock *clk =
495 (struct exynos4_clock *)samsung_get_base_clock();
496 unsigned long pclk, sclk;
500 if (s5p_get_cpu_rev() == 0) {
505 sel = readl(&clk->src_peril0);
506 sel = (sel >> 24) & 0xf;
509 sclk = get_pll_clk(MPLL);
511 sclk = get_pll_clk(EPLL);
513 sclk = get_pll_clk(VPLL);
521 ratio = readl(&clk->div_peril3);
523 } else if (s5p_get_cpu_rev() == 1) {
524 sclk = get_pll_clk(MPLL);
529 pclk = sclk / (ratio + 1);
534 /* exynos4x12: return pwm clock frequency */
535 static unsigned long exynos4x12_get_pwm_clk(void)
537 unsigned long pclk, sclk;
540 sclk = get_pll_clk(MPLL);
543 pclk = sclk / (ratio + 1);
548 /* exynos5420: return pwm clock frequency */
549 static unsigned long exynos5420_get_pwm_clk(void)
551 struct exynos5420_clock *clk =
552 (struct exynos5420_clock *)samsung_get_base_clock();
553 unsigned long pclk, sclk;
560 ratio = readl(&clk->div_peric0);
561 ratio = (ratio >> 28) & 0xf;
562 sclk = get_pll_clk(MPLL);
564 pclk = sclk / (ratio + 1);
569 /* exynos4: return uart clock frequency */
570 static unsigned long exynos4_get_uart_clk(int dev_index)
572 struct exynos4_clock *clk =
573 (struct exynos4_clock *)samsung_get_base_clock();
574 unsigned long uclk, sclk;
587 sel = readl(&clk->src_peril0);
588 sel = (sel >> (dev_index << 2)) & 0xf;
591 sclk = get_pll_clk(MPLL);
593 sclk = get_pll_clk(EPLL);
595 sclk = get_pll_clk(VPLL);
604 * UART3_RATIO [12:15]
605 * UART4_RATIO [16:19]
606 * UART5_RATIO [23:20]
608 ratio = readl(&clk->div_peril0);
609 ratio = (ratio >> (dev_index << 2)) & 0xf;
611 uclk = sclk / (ratio + 1);
616 /* exynos4x12: return uart clock frequency */
617 static unsigned long exynos4x12_get_uart_clk(int dev_index)
619 struct exynos4x12_clock *clk =
620 (struct exynos4x12_clock *)samsung_get_base_clock();
621 unsigned long uclk, sclk;
633 sel = readl(&clk->src_peril0);
634 sel = (sel >> (dev_index << 2)) & 0xf;
637 sclk = get_pll_clk(MPLL);
639 sclk = get_pll_clk(EPLL);
641 sclk = get_pll_clk(VPLL);
650 * UART3_RATIO [12:15]
651 * UART4_RATIO [16:19]
653 ratio = readl(&clk->div_peril0);
654 ratio = (ratio >> (dev_index << 2)) & 0xf;
656 uclk = sclk / (ratio + 1);
661 /* exynos5: return uart clock frequency */
662 static unsigned long exynos5_get_uart_clk(int dev_index)
664 struct exynos5_clock *clk =
665 (struct exynos5_clock *)samsung_get_base_clock();
666 unsigned long uclk, sclk;
679 sel = readl(&clk->src_peric0);
680 sel = (sel >> (dev_index << 2)) & 0xf;
683 sclk = get_pll_clk(MPLL);
685 sclk = get_pll_clk(EPLL);
687 sclk = get_pll_clk(VPLL);
696 * UART3_RATIO [12:15]
697 * UART4_RATIO [16:19]
698 * UART5_RATIO [23:20]
700 ratio = readl(&clk->div_peric0);
701 ratio = (ratio >> (dev_index << 2)) & 0xf;
703 uclk = sclk / (ratio + 1);
708 /* exynos5420: return uart clock frequency */
709 static unsigned long exynos5420_get_uart_clk(int dev_index)
711 struct exynos5420_clock *clk =
712 (struct exynos5420_clock *)samsung_get_base_clock();
713 unsigned long uclk, sclk;
723 * generalised calculation as follows
724 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
726 sel = readl(&clk->src_peric0);
727 sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
730 sclk = get_pll_clk(MPLL);
732 sclk = get_pll_clk(EPLL);
734 sclk = get_pll_clk(RPLL);
741 * UART1_RATIO [15:12]
742 * UART2_RATIO [19:16]
743 * UART3_RATIO [23:20]
744 * generalised calculation as follows
745 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
747 ratio = readl(&clk->div_peric0);
748 ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
750 uclk = sclk / (ratio + 1);
755 static unsigned long exynos4_get_mmc_clk(int dev_index)
757 struct exynos4_clock *clk =
758 (struct exynos4_clock *)samsung_get_base_clock();
759 unsigned long uclk, sclk;
760 unsigned int sel, ratio, pre_ratio;
763 sel = readl(&clk->src_fsys);
764 sel = (sel >> (dev_index << 2)) & 0xf;
767 sclk = get_pll_clk(MPLL);
769 sclk = get_pll_clk(EPLL);
771 sclk = get_pll_clk(VPLL);
778 ratio = readl(&clk->div_fsys1);
779 pre_ratio = readl(&clk->div_fsys1);
783 ratio = readl(&clk->div_fsys2);
784 pre_ratio = readl(&clk->div_fsys2);
787 ratio = readl(&clk->div_fsys3);
788 pre_ratio = readl(&clk->div_fsys3);
794 if (dev_index == 1 || dev_index == 3)
797 ratio = (ratio >> shift) & 0xf;
798 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
799 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
804 static unsigned long exynos5_get_mmc_clk(int dev_index)
806 struct exynos5_clock *clk =
807 (struct exynos5_clock *)samsung_get_base_clock();
808 unsigned long uclk, sclk;
809 unsigned int sel, ratio, pre_ratio;
812 sel = readl(&clk->src_fsys);
813 sel = (sel >> (dev_index << 2)) & 0xf;
816 sclk = get_pll_clk(MPLL);
818 sclk = get_pll_clk(EPLL);
820 sclk = get_pll_clk(VPLL);
827 ratio = readl(&clk->div_fsys1);
828 pre_ratio = readl(&clk->div_fsys1);
832 ratio = readl(&clk->div_fsys2);
833 pre_ratio = readl(&clk->div_fsys2);
839 if (dev_index == 1 || dev_index == 3)
842 ratio = (ratio >> shift) & 0xf;
843 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
844 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
849 static unsigned long exynos5420_get_mmc_clk(int dev_index)
851 struct exynos5420_clock *clk =
852 (struct exynos5420_clock *)samsung_get_base_clock();
853 unsigned long uclk, sclk;
854 unsigned int sel, ratio;
861 * generalised calculation as follows
862 * sel = (sel >> ((dev_index * 4) + 8)) & mask
864 sel = readl(&clk->src_fsys);
865 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
868 sclk = get_pll_clk(MPLL);
870 sclk = get_pll_clk(SPLL);
872 sclk = get_pll_clk(EPLL);
881 * generalised calculation as follows
882 * ratio = (ratio >> (dev_index * 10)) & mask
884 ratio = readl(&clk->div_fsys1);
885 ratio = (ratio >> (dev_index * 10)) & 0x3ff;
887 uclk = (sclk / (ratio + 1));
892 /* exynos4: set the mmc clock */
893 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
895 struct exynos4_clock *clk =
896 (struct exynos4_clock *)samsung_get_base_clock();
897 unsigned int addr, clear_bit, set_bit;
901 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
903 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
908 addr = (unsigned int)&clk->div_fsys1;
909 clear_bit = MASK_PRE_RATIO(dev_index);
910 set_bit = SET_PRE_RATIO(dev_index, div);
911 } else if (dev_index == 4) {
912 addr = (unsigned int)&clk->div_fsys3;
914 /* MMC4 is controlled with the MMC4_RATIO value */
915 clear_bit = MASK_RATIO(dev_index);
916 set_bit = SET_RATIO(dev_index, div);
918 addr = (unsigned int)&clk->div_fsys2;
920 clear_bit = MASK_PRE_RATIO(dev_index);
921 set_bit = SET_PRE_RATIO(dev_index, div);
924 clrsetbits_le32(addr, clear_bit, set_bit);
927 /* exynos5: set the mmc clock */
928 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
930 struct exynos5_clock *clk =
931 (struct exynos5_clock *)samsung_get_base_clock();
936 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
938 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
941 addr = (unsigned int)&clk->div_fsys1;
943 addr = (unsigned int)&clk->div_fsys2;
947 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
948 (div & 0xff) << ((dev_index << 4) + 8));
951 /* exynos5: set the mmc clock */
952 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
954 struct exynos5420_clock *clk =
955 (struct exynos5420_clock *)samsung_get_base_clock();
965 addr = (unsigned int)&clk->div_fsys1;
966 shift = dev_index * 10;
968 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
971 /* get_lcd_clk: return lcd clock frequency */
972 static unsigned long exynos4_get_lcd_clk(void)
974 struct exynos4_clock *clk =
975 (struct exynos4_clock *)samsung_get_base_clock();
976 unsigned long pclk, sclk;
984 sel = readl(&clk->src_lcd0);
993 sclk = get_pll_clk(MPLL);
995 sclk = get_pll_clk(EPLL);
997 sclk = get_pll_clk(VPLL);
1005 ratio = readl(&clk->div_lcd0);
1006 ratio = ratio & 0xf;
1008 pclk = sclk / (ratio + 1);
1013 /* get_lcd_clk: return lcd clock frequency */
1014 static unsigned long exynos5_get_lcd_clk(void)
1016 struct exynos5_clock *clk =
1017 (struct exynos5_clock *)samsung_get_base_clock();
1018 unsigned long pclk, sclk;
1026 sel = readl(&clk->src_disp1_0);
1035 sclk = get_pll_clk(MPLL);
1036 else if (sel == 0x7)
1037 sclk = get_pll_clk(EPLL);
1038 else if (sel == 0x8)
1039 sclk = get_pll_clk(VPLL);
1047 ratio = readl(&clk->div_disp1_0);
1048 ratio = ratio & 0xf;
1050 pclk = sclk / (ratio + 1);
1055 static unsigned long exynos5420_get_lcd_clk(void)
1057 struct exynos5420_clock *clk =
1058 (struct exynos5420_clock *)samsung_get_base_clock();
1059 unsigned long pclk, sclk;
1069 sel = readl(&clk->src_disp10);
1073 sclk = get_pll_clk(SPLL);
1075 sclk = get_pll_clk(RPLL);
1081 ratio = readl(&clk->div_disp10);
1082 ratio = ratio & 0xf;
1084 pclk = sclk / (ratio + 1);
1089 void exynos4_set_lcd_clk(void)
1091 struct exynos4_clock *clk =
1092 (struct exynos4_clock *)samsung_get_base_clock();
1104 setbits_le32(&clk->gate_block, 1 << 4);
1110 * MDNIE_PWM0_SEL [8:11]
1112 * set lcd0 src clock 0x6: SCLK_MPLL
1114 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
1124 * Gating all clocks for FIMD0
1126 setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
1131 * MDNIE0_RATIO [7:4]
1132 * MDNIE_PWM0_RATIO [11:8]
1133 * MDNIE_PWM_PRE_RATIO [15:12]
1134 * MIPI0_RATIO [19:16]
1135 * MIPI0_PRE_RATIO [23:20]
1138 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
1141 void exynos5_set_lcd_clk(void)
1143 struct exynos5_clock *clk =
1144 (struct exynos5_clock *)samsung_get_base_clock();
1156 setbits_le32(&clk->gate_block, 1 << 4);
1162 * MDNIE_PWM0_SEL [8:11]
1164 * set lcd0 src clock 0x6: SCLK_MPLL
1166 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
1176 * Gating all clocks for FIMD0
1178 setbits_le32(&clk->gate_ip_disp1, 1 << 0);
1183 * MDNIE0_RATIO [7:4]
1184 * MDNIE_PWM0_RATIO [11:8]
1185 * MDNIE_PWM_PRE_RATIO [15:12]
1186 * MIPI0_RATIO [19:16]
1187 * MIPI0_PRE_RATIO [23:20]
1190 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1193 void exynos5420_set_lcd_clk(void)
1195 struct exynos5420_clock *clk =
1196 (struct exynos5420_clock *)samsung_get_base_clock();
1205 cfg = readl(&clk->src_disp10);
1208 writel(cfg, &clk->src_disp10);
1214 cfg = readl(&clk->div_disp10);
1217 writel(cfg, &clk->div_disp10);
1220 void exynos4_set_mipi_clk(void)
1222 struct exynos4_clock *clk =
1223 (struct exynos4_clock *)samsung_get_base_clock();
1229 * MDNIE_PWM0_SEL [8:11]
1231 * set mipi0 src clock 0x6: SCLK_MPLL
1233 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
1239 * MDNIE_PWM0_MASK [8]
1241 * set src mask mipi0 0x1: Unmask
1243 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
1253 * Gating all clocks for MIPI0
1255 setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
1260 * MDNIE0_RATIO [7:4]
1261 * MDNIE_PWM0_RATIO [11:8]
1262 * MDNIE_PWM_PRE_RATIO [15:12]
1263 * MIPI0_RATIO [19:16]
1264 * MIPI0_PRE_RATIO [23:20]
1267 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
1273 * exynos5: obtaining the I2C clock
1275 static unsigned long exynos5_get_i2c_clk(void)
1277 struct exynos5_clock *clk =
1278 (struct exynos5_clock *)samsung_get_base_clock();
1279 unsigned long aclk_66, aclk_66_pre, sclk;
1282 sclk = get_pll_clk(MPLL);
1284 ratio = (readl(&clk->div_top1)) >> 24;
1286 aclk_66_pre = sclk / (ratio + 1);
1287 ratio = readl(&clk->div_top0);
1289 aclk_66 = aclk_66_pre / (ratio + 1);
1293 int exynos5_set_epll_clk(unsigned long rate)
1295 unsigned int epll_con, epll_con_k;
1297 unsigned int lockcnt;
1299 struct exynos5_clock *clk =
1300 (struct exynos5_clock *)samsung_get_base_clock();
1302 epll_con = readl(&clk->epll_con0);
1303 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1304 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1305 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1306 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1307 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1309 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1310 if (exynos5_epll_div[i].freq_out == rate)
1314 if (i == ARRAY_SIZE(exynos5_epll_div))
1317 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1318 epll_con |= exynos5_epll_div[i].en_lock_det <<
1319 EPLL_CON0_LOCK_DET_EN_SHIFT;
1320 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1321 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1322 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1325 * Required period ( in cycles) to genarate a stable clock output.
1326 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1327 * frequency input (as per spec)
1329 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1331 writel(lockcnt, &clk->epll_lock);
1332 writel(epll_con, &clk->epll_con0);
1333 writel(epll_con_k, &clk->epll_con1);
1335 start = get_timer(0);
1337 while (!(readl(&clk->epll_con0) &
1338 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1339 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1340 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1347 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1349 struct exynos5_clock *clk =
1350 (struct exynos5_clock *)samsung_get_base_clock();
1351 unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1354 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1355 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1356 (CLK_SRC_SCLK_EPLL));
1357 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1358 } else if (i2s_id == 1) {
1359 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1360 (CLK_SRC_SCLK_EPLL));
1367 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1368 unsigned int dst_frq,
1369 unsigned int i2s_id)
1371 struct exynos5_clock *clk =
1372 (struct exynos5_clock *)samsung_get_base_clock();
1375 if ((dst_frq == 0) || (src_frq == 0)) {
1376 debug("%s: Invalid requency input for prescaler\n", __func__);
1377 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1381 div = (src_frq / dst_frq);
1383 if (div > AUDIO_0_RATIO_MASK) {
1384 debug("%s: Frequency ratio is out of range\n",
1386 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1389 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1390 (div & AUDIO_0_RATIO_MASK));
1391 } else if(i2s_id == 1) {
1392 if (div > AUDIO_1_RATIO_MASK) {
1393 debug("%s: Frequency ratio is out of range\n",
1395 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1398 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1399 (div & AUDIO_1_RATIO_MASK));
1407 * Linearly searches for the most accurate main and fine stage clock scalars
1408 * (divisors) for a specified target frequency and scalar bit sizes by checking
1409 * all multiples of main_scalar_bits values. Will always return scalars up to or
1410 * slower than target.
1412 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1413 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1414 * @param input_freq Clock frequency to be scaled in Hz
1415 * @param target_freq Desired clock frequency in Hz
1416 * @param best_fine_scalar Pointer to store the fine stage divisor
1418 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1421 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1422 unsigned int fine_scalar_bits, unsigned int input_rate,
1423 unsigned int target_rate, unsigned int *best_fine_scalar)
1426 int best_main_scalar = -1;
1427 unsigned int best_error = target_rate;
1428 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1429 const unsigned int loops = 1 << main_scaler_bits;
1431 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1434 assert(best_fine_scalar != NULL);
1435 assert(main_scaler_bits <= fine_scalar_bits);
1437 *best_fine_scalar = 1;
1439 if (input_rate == 0 || target_rate == 0)
1442 if (target_rate >= input_rate)
1445 for (i = 1; i <= loops; i++) {
1446 const unsigned int effective_div =
1447 max(min(input_rate / i / target_rate, cap), 1U);
1448 const unsigned int effective_rate = input_rate / i /
1450 const int error = target_rate - effective_rate;
1452 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1453 effective_rate, error);
1455 if (error >= 0 && error <= best_error) {
1457 best_main_scalar = i;
1458 *best_fine_scalar = effective_div;
1462 return best_main_scalar;
1465 static int exynos5_set_spi_clk(enum periph_id periph_id,
1468 struct exynos5_clock *clk =
1469 (struct exynos5_clock *)samsung_get_base_clock();
1472 unsigned shift, pre_shift;
1473 unsigned mask = 0xff;
1476 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1478 debug("%s: Cannot set clock rate for periph %d",
1479 __func__, periph_id);
1485 switch (periph_id) {
1486 case PERIPH_ID_SPI0:
1487 reg = &clk->div_peric1;
1491 case PERIPH_ID_SPI1:
1492 reg = &clk->div_peric1;
1496 case PERIPH_ID_SPI2:
1497 reg = &clk->div_peric2;
1501 case PERIPH_ID_SPI3:
1502 reg = &clk->sclk_div_isp;
1506 case PERIPH_ID_SPI4:
1507 reg = &clk->sclk_div_isp;
1512 debug("%s: Unsupported peripheral ID %d\n", __func__,
1516 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1517 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1522 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1525 struct exynos5420_clock *clk =
1526 (struct exynos5420_clock *)samsung_get_base_clock();
1529 unsigned shift, pre_shift;
1530 unsigned div_mask = 0xf, pre_div_mask = 0xff;
1534 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1536 debug("%s: Cannot set clock rate for periph %d",
1537 __func__, periph_id);
1543 switch (periph_id) {
1544 case PERIPH_ID_SPI0:
1545 reg = &clk->div_peric1;
1547 pre_reg = &clk->div_peric4;
1550 case PERIPH_ID_SPI1:
1551 reg = &clk->div_peric1;
1553 pre_reg = &clk->div_peric4;
1556 case PERIPH_ID_SPI2:
1557 reg = &clk->div_peric1;
1559 pre_reg = &clk->div_peric4;
1562 case PERIPH_ID_SPI3:
1563 reg = &clk->div_isp1;
1565 pre_reg = &clk->div_isp1;
1568 case PERIPH_ID_SPI4:
1569 reg = &clk->div_isp1;
1571 pre_reg = &clk->div_isp1;
1575 debug("%s: Unsupported peripheral ID %d\n", __func__,
1580 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1581 clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1582 (fine & pre_div_mask) << pre_shift);
1587 static unsigned long exynos4_get_i2c_clk(void)
1589 struct exynos4_clock *clk =
1590 (struct exynos4_clock *)samsung_get_base_clock();
1591 unsigned long sclk, aclk_100;
1594 sclk = get_pll_clk(APLL);
1596 ratio = (readl(&clk->div_top)) >> 4;
1598 aclk_100 = sclk / (ratio + 1);
1602 unsigned long get_pll_clk(int pllreg)
1604 if (cpu_is_exynos5()) {
1605 if (proid_is_exynos5420() || proid_is_exynos5800())
1606 return exynos542x_get_pll_clk(pllreg);
1607 return exynos5_get_pll_clk(pllreg);
1609 if (proid_is_exynos4412())
1610 return exynos4x12_get_pll_clk(pllreg);
1611 return exynos4_get_pll_clk(pllreg);
1615 unsigned long get_arm_clk(void)
1617 if (cpu_is_exynos5())
1618 return exynos5_get_arm_clk();
1620 if (proid_is_exynos4412())
1621 return exynos4x12_get_arm_clk();
1622 return exynos4_get_arm_clk();
1626 unsigned long get_i2c_clk(void)
1628 if (cpu_is_exynos5()) {
1629 return exynos5_get_i2c_clk();
1630 } else if (cpu_is_exynos4()) {
1631 return exynos4_get_i2c_clk();
1633 debug("I2C clock is not set for this CPU\n");
1638 unsigned long get_pwm_clk(void)
1640 if (cpu_is_exynos5()) {
1641 if (proid_is_exynos5420() || proid_is_exynos5800())
1642 return exynos5420_get_pwm_clk();
1643 return clock_get_periph_rate(PERIPH_ID_PWM0);
1645 if (proid_is_exynos4412())
1646 return exynos4x12_get_pwm_clk();
1647 return exynos4_get_pwm_clk();
1651 unsigned long get_uart_clk(int dev_index)
1653 if (cpu_is_exynos5()) {
1654 if (proid_is_exynos5420() || proid_is_exynos5800())
1655 return exynos5420_get_uart_clk(dev_index);
1656 return exynos5_get_uart_clk(dev_index);
1658 if (proid_is_exynos4412())
1659 return exynos4x12_get_uart_clk(dev_index);
1660 return exynos4_get_uart_clk(dev_index);
1664 unsigned long get_mmc_clk(int dev_index)
1666 if (cpu_is_exynos5()) {
1667 if (proid_is_exynos5420() || proid_is_exynos5800())
1668 return exynos5420_get_mmc_clk(dev_index);
1669 return exynos5_get_mmc_clk(dev_index);
1671 return exynos4_get_mmc_clk(dev_index);
1675 void set_mmc_clk(int dev_index, unsigned int div)
1677 /* If want to set correct value, it needs to substract one from div.*/
1681 if (cpu_is_exynos5()) {
1682 if (proid_is_exynos5420() || proid_is_exynos5800())
1683 exynos5420_set_mmc_clk(dev_index, div);
1685 exynos5_set_mmc_clk(dev_index, div);
1687 exynos4_set_mmc_clk(dev_index, div);
1691 unsigned long get_lcd_clk(void)
1693 if (cpu_is_exynos4())
1694 return exynos4_get_lcd_clk();
1696 if (proid_is_exynos5420() || proid_is_exynos5800())
1697 return exynos5420_get_lcd_clk();
1699 return exynos5_get_lcd_clk();
1703 void set_lcd_clk(void)
1705 if (cpu_is_exynos4())
1706 exynos4_set_lcd_clk();
1708 if (proid_is_exynos5250())
1709 exynos5_set_lcd_clk();
1710 else if (proid_is_exynos5420() || proid_is_exynos5800())
1711 exynos5420_set_lcd_clk();
1715 void set_mipi_clk(void)
1717 if (cpu_is_exynos4())
1718 exynos4_set_mipi_clk();
1721 int set_spi_clk(int periph_id, unsigned int rate)
1723 if (cpu_is_exynos5()) {
1724 if (proid_is_exynos5420() || proid_is_exynos5800())
1725 return exynos5420_set_spi_clk(periph_id, rate);
1726 return exynos5_set_spi_clk(periph_id, rate);
1732 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1733 unsigned int i2s_id)
1735 if (cpu_is_exynos5())
1736 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1741 int set_i2s_clk_source(unsigned int i2s_id)
1743 if (cpu_is_exynos5())
1744 return exynos5_set_i2s_clk_source(i2s_id);
1749 int set_epll_clk(unsigned long rate)
1751 if (cpu_is_exynos5())
1752 return exynos5_set_epll_clk(rate);