2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/periph.h>
14 #define PLL_DIV_1024 1024
15 #define PLL_DIV_65535 65535
16 #define PLL_DIV_65536 65536
19 * This structure is to store the src bit, div bit and prediv bit
20 * positions of the peripheral clocks of the src and div registers
28 /* src_bit div_bit prediv_bit */
29 static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
61 /* Epll Clock division values to achive different frequency output */
62 static struct set_epll_con_val exynos5_epll_div[] = {
63 { 192000000, 0, 48, 3, 1, 0 },
64 { 180000000, 0, 45, 3, 1, 0 },
65 { 73728000, 1, 73, 3, 3, 47710 },
66 { 67737600, 1, 90, 4, 3, 20762 },
67 { 49152000, 0, 49, 3, 3, 9961 },
68 { 45158400, 0, 45, 3, 3, 10381 },
69 { 180633600, 0, 45, 3, 1, 10381 }
72 /* exynos: return pll clock frequency */
73 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
75 unsigned long m, p, s = 0, mask, fout;
79 * APLL_CON: MIDV [25:16]
80 * MPLL_CON: MIDV [25:16]
81 * EPLL_CON: MIDV [24:16]
82 * VPLL_CON: MIDV [24:16]
83 * BPLL_CON: MIDV [25:16]: Exynos5
85 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
97 freq = CONFIG_SYS_CLK_FREQ;
101 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
102 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
103 } else if (pllreg == VPLL) {
108 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
111 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
114 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
116 if (proid_is_exynos4210())
118 else if (proid_is_exynos4412())
120 else if (proid_is_exynos5250())
125 fout = (m + k / div) * (freq / (p * (1 << s)));
128 * Exynos4412 / Exynos5250
129 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
132 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
134 if (proid_is_exynos4210())
135 fout = m * (freq / (p * (1 << (s - 1))));
137 fout = m * (freq / (p * (1 << s)));
142 /* exynos4: return pll clock frequency */
143 static unsigned long exynos4_get_pll_clk(int pllreg)
145 struct exynos4_clock *clk =
146 (struct exynos4_clock *)samsung_get_base_clock();
147 unsigned long r, k = 0;
151 r = readl(&clk->apll_con0);
154 r = readl(&clk->mpll_con0);
157 r = readl(&clk->epll_con0);
158 k = readl(&clk->epll_con1);
161 r = readl(&clk->vpll_con0);
162 k = readl(&clk->vpll_con1);
165 printf("Unsupported PLL (%d)\n", pllreg);
169 return exynos_get_pll_clk(pllreg, r, k);
172 /* exynos4x12: return pll clock frequency */
173 static unsigned long exynos4x12_get_pll_clk(int pllreg)
175 struct exynos4x12_clock *clk =
176 (struct exynos4x12_clock *)samsung_get_base_clock();
177 unsigned long r, k = 0;
181 r = readl(&clk->apll_con0);
184 r = readl(&clk->mpll_con0);
187 r = readl(&clk->epll_con0);
188 k = readl(&clk->epll_con1);
191 r = readl(&clk->vpll_con0);
192 k = readl(&clk->vpll_con1);
195 printf("Unsupported PLL (%d)\n", pllreg);
199 return exynos_get_pll_clk(pllreg, r, k);
202 /* exynos5: return pll clock frequency */
203 static unsigned long exynos5_get_pll_clk(int pllreg)
205 struct exynos5_clock *clk =
206 (struct exynos5_clock *)samsung_get_base_clock();
207 unsigned long r, k = 0, fout;
208 unsigned int pll_div2_sel, fout_sel;
212 r = readl(&clk->apll_con0);
215 r = readl(&clk->mpll_con0);
218 r = readl(&clk->epll_con0);
219 k = readl(&clk->epll_con1);
222 r = readl(&clk->vpll_con0);
223 k = readl(&clk->vpll_con1);
226 r = readl(&clk->bpll_con0);
229 printf("Unsupported PLL (%d)\n", pllreg);
233 fout = exynos_get_pll_clk(pllreg, r, k);
235 /* According to the user manual, in EVT1 MPLL and BPLL always gives
236 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
237 if (pllreg == MPLL || pllreg == BPLL) {
238 pll_div2_sel = readl(&clk->pll_div2_sel);
242 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
243 & MPLL_FOUT_SEL_MASK;
246 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
247 & BPLL_FOUT_SEL_MASK;
261 static unsigned long exynos5_get_periph_rate(int peripheral)
263 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
264 unsigned long sclk, sub_clk;
265 unsigned int src, div, sub_div;
266 struct exynos5_clock *clk =
267 (struct exynos5_clock *)samsung_get_base_clock();
269 switch (peripheral) {
270 case PERIPH_ID_UART0:
271 case PERIPH_ID_UART1:
272 case PERIPH_ID_UART2:
273 case PERIPH_ID_UART3:
274 src = readl(&clk->src_peric0);
275 div = readl(&clk->div_peric0);
282 src = readl(&clk->src_peric0);
283 div = readl(&clk->div_peric3);
287 src = readl(&clk->src_peric1);
288 div = readl(&clk->div_peric1);
291 src = readl(&clk->src_peric1);
292 div = readl(&clk->div_peric2);
296 src = readl(&clk->sclk_src_isp);
297 div = readl(&clk->sclk_div_isp);
299 case PERIPH_ID_SDMMC0:
300 case PERIPH_ID_SDMMC1:
301 case PERIPH_ID_SDMMC2:
302 case PERIPH_ID_SDMMC3:
303 src = readl(&clk->src_fsys);
304 div = readl(&clk->div_fsys1);
314 sclk = exynos5_get_pll_clk(MPLL);
315 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
317 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
319 return (sclk / sub_div) / div;
321 debug("%s: invalid peripheral %d", __func__, peripheral);
325 src = (src >> bit_info->src_bit) & 0xf;
328 case EXYNOS_SRC_MPLL:
329 sclk = exynos5_get_pll_clk(MPLL);
331 case EXYNOS_SRC_EPLL:
332 sclk = exynos5_get_pll_clk(EPLL);
334 case EXYNOS_SRC_VPLL:
335 sclk = exynos5_get_pll_clk(VPLL);
341 /* Ratio clock division for this peripheral */
342 sub_div = (div >> bit_info->div_bit) & 0xf;
343 sub_clk = sclk / (sub_div + 1);
345 /* Pre-ratio clock division for SDMMC0 and 2 */
346 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
347 div = (div >> bit_info->prediv_bit) & 0xff;
348 return sub_clk / (div + 1);
354 unsigned long clock_get_periph_rate(int peripheral)
356 if (cpu_is_exynos5())
357 return exynos5_get_periph_rate(peripheral);
362 /* exynos4: return ARM clock frequency */
363 static unsigned long exynos4_get_arm_clk(void)
365 struct exynos4_clock *clk =
366 (struct exynos4_clock *)samsung_get_base_clock();
368 unsigned long armclk;
369 unsigned int core_ratio;
370 unsigned int core2_ratio;
372 div = readl(&clk->div_cpu0);
374 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
375 core_ratio = (div >> 0) & 0x7;
376 core2_ratio = (div >> 28) & 0x7;
378 armclk = get_pll_clk(APLL) / (core_ratio + 1);
379 armclk /= (core2_ratio + 1);
384 /* exynos4x12: return ARM clock frequency */
385 static unsigned long exynos4x12_get_arm_clk(void)
387 struct exynos4x12_clock *clk =
388 (struct exynos4x12_clock *)samsung_get_base_clock();
390 unsigned long armclk;
391 unsigned int core_ratio;
392 unsigned int core2_ratio;
394 div = readl(&clk->div_cpu0);
396 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
397 core_ratio = (div >> 0) & 0x7;
398 core2_ratio = (div >> 28) & 0x7;
400 armclk = get_pll_clk(APLL) / (core_ratio + 1);
401 armclk /= (core2_ratio + 1);
406 /* exynos5: return ARM clock frequency */
407 static unsigned long exynos5_get_arm_clk(void)
409 struct exynos5_clock *clk =
410 (struct exynos5_clock *)samsung_get_base_clock();
412 unsigned long armclk;
413 unsigned int arm_ratio;
414 unsigned int arm2_ratio;
416 div = readl(&clk->div_cpu0);
418 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
419 arm_ratio = (div >> 0) & 0x7;
420 arm2_ratio = (div >> 28) & 0x7;
422 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
423 armclk /= (arm2_ratio + 1);
428 /* exynos4: return pwm clock frequency */
429 static unsigned long exynos4_get_pwm_clk(void)
431 struct exynos4_clock *clk =
432 (struct exynos4_clock *)samsung_get_base_clock();
433 unsigned long pclk, sclk;
437 if (s5p_get_cpu_rev() == 0) {
442 sel = readl(&clk->src_peril0);
443 sel = (sel >> 24) & 0xf;
446 sclk = get_pll_clk(MPLL);
448 sclk = get_pll_clk(EPLL);
450 sclk = get_pll_clk(VPLL);
458 ratio = readl(&clk->div_peril3);
460 } else if (s5p_get_cpu_rev() == 1) {
461 sclk = get_pll_clk(MPLL);
466 pclk = sclk / (ratio + 1);
471 /* exynos4x12: return pwm clock frequency */
472 static unsigned long exynos4x12_get_pwm_clk(void)
474 unsigned long pclk, sclk;
477 sclk = get_pll_clk(MPLL);
480 pclk = sclk / (ratio + 1);
485 /* exynos4: return uart clock frequency */
486 static unsigned long exynos4_get_uart_clk(int dev_index)
488 struct exynos4_clock *clk =
489 (struct exynos4_clock *)samsung_get_base_clock();
490 unsigned long uclk, sclk;
503 sel = readl(&clk->src_peril0);
504 sel = (sel >> (dev_index << 2)) & 0xf;
507 sclk = get_pll_clk(MPLL);
509 sclk = get_pll_clk(EPLL);
511 sclk = get_pll_clk(VPLL);
520 * UART3_RATIO [12:15]
521 * UART4_RATIO [16:19]
522 * UART5_RATIO [23:20]
524 ratio = readl(&clk->div_peril0);
525 ratio = (ratio >> (dev_index << 2)) & 0xf;
527 uclk = sclk / (ratio + 1);
532 /* exynos4x12: return uart clock frequency */
533 static unsigned long exynos4x12_get_uart_clk(int dev_index)
535 struct exynos4x12_clock *clk =
536 (struct exynos4x12_clock *)samsung_get_base_clock();
537 unsigned long uclk, sclk;
549 sel = readl(&clk->src_peril0);
550 sel = (sel >> (dev_index << 2)) & 0xf;
553 sclk = get_pll_clk(MPLL);
555 sclk = get_pll_clk(EPLL);
557 sclk = get_pll_clk(VPLL);
566 * UART3_RATIO [12:15]
567 * UART4_RATIO [16:19]
569 ratio = readl(&clk->div_peril0);
570 ratio = (ratio >> (dev_index << 2)) & 0xf;
572 uclk = sclk / (ratio + 1);
577 /* exynos5: return uart clock frequency */
578 static unsigned long exynos5_get_uart_clk(int dev_index)
580 struct exynos5_clock *clk =
581 (struct exynos5_clock *)samsung_get_base_clock();
582 unsigned long uclk, sclk;
595 sel = readl(&clk->src_peric0);
596 sel = (sel >> (dev_index << 2)) & 0xf;
599 sclk = get_pll_clk(MPLL);
601 sclk = get_pll_clk(EPLL);
603 sclk = get_pll_clk(VPLL);
612 * UART3_RATIO [12:15]
613 * UART4_RATIO [16:19]
614 * UART5_RATIO [23:20]
616 ratio = readl(&clk->div_peric0);
617 ratio = (ratio >> (dev_index << 2)) & 0xf;
619 uclk = sclk / (ratio + 1);
624 static unsigned long exynos4_get_mmc_clk(int dev_index)
626 struct exynos4_clock *clk =
627 (struct exynos4_clock *)samsung_get_base_clock();
628 unsigned long uclk, sclk;
629 unsigned int sel, ratio, pre_ratio;
632 sel = readl(&clk->src_fsys);
633 sel = (sel >> (dev_index << 2)) & 0xf;
636 sclk = get_pll_clk(MPLL);
638 sclk = get_pll_clk(EPLL);
640 sclk = get_pll_clk(VPLL);
647 ratio = readl(&clk->div_fsys1);
648 pre_ratio = readl(&clk->div_fsys1);
652 ratio = readl(&clk->div_fsys2);
653 pre_ratio = readl(&clk->div_fsys2);
656 ratio = readl(&clk->div_fsys3);
657 pre_ratio = readl(&clk->div_fsys3);
663 if (dev_index == 1 || dev_index == 3)
666 ratio = (ratio >> shift) & 0xf;
667 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
668 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
673 static unsigned long exynos5_get_mmc_clk(int dev_index)
675 struct exynos5_clock *clk =
676 (struct exynos5_clock *)samsung_get_base_clock();
677 unsigned long uclk, sclk;
678 unsigned int sel, ratio, pre_ratio;
681 sel = readl(&clk->src_fsys);
682 sel = (sel >> (dev_index << 2)) & 0xf;
685 sclk = get_pll_clk(MPLL);
687 sclk = get_pll_clk(EPLL);
689 sclk = get_pll_clk(VPLL);
696 ratio = readl(&clk->div_fsys1);
697 pre_ratio = readl(&clk->div_fsys1);
701 ratio = readl(&clk->div_fsys2);
702 pre_ratio = readl(&clk->div_fsys2);
708 if (dev_index == 1 || dev_index == 3)
711 ratio = (ratio >> shift) & 0xf;
712 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
713 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
718 /* exynos4: set the mmc clock */
719 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
721 struct exynos4_clock *clk =
722 (struct exynos4_clock *)samsung_get_base_clock();
728 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
730 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
732 * MMC4_PRE_RATIO [15:8]
735 addr = (unsigned int)&clk->div_fsys1;
736 } else if (dev_index == 4) {
737 addr = (unsigned int)&clk->div_fsys3;
740 addr = (unsigned int)&clk->div_fsys2;
745 val &= ~(0xff << ((dev_index << 4) + 8));
746 val |= (div & 0xff) << ((dev_index << 4) + 8);
750 /* exynos4x12: set the mmc clock */
751 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
753 struct exynos4x12_clock *clk =
754 (struct exynos4x12_clock *)samsung_get_base_clock();
760 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
762 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
765 addr = (unsigned int)&clk->div_fsys1;
767 addr = (unsigned int)&clk->div_fsys2;
772 val &= ~(0xff << ((dev_index << 4) + 8));
773 val |= (div & 0xff) << ((dev_index << 4) + 8);
777 /* exynos5: set the mmc clock */
778 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
780 struct exynos5_clock *clk =
781 (struct exynos5_clock *)samsung_get_base_clock();
787 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
789 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
792 addr = (unsigned int)&clk->div_fsys1;
794 addr = (unsigned int)&clk->div_fsys2;
799 val &= ~(0xff << ((dev_index << 4) + 8));
800 val |= (div & 0xff) << ((dev_index << 4) + 8);
804 /* get_lcd_clk: return lcd clock frequency */
805 static unsigned long exynos4_get_lcd_clk(void)
807 struct exynos4_clock *clk =
808 (struct exynos4_clock *)samsung_get_base_clock();
809 unsigned long pclk, sclk;
817 sel = readl(&clk->src_lcd0);
826 sclk = get_pll_clk(MPLL);
828 sclk = get_pll_clk(EPLL);
830 sclk = get_pll_clk(VPLL);
838 ratio = readl(&clk->div_lcd0);
841 pclk = sclk / (ratio + 1);
846 /* get_lcd_clk: return lcd clock frequency */
847 static unsigned long exynos5_get_lcd_clk(void)
849 struct exynos5_clock *clk =
850 (struct exynos5_clock *)samsung_get_base_clock();
851 unsigned long pclk, sclk;
859 sel = readl(&clk->src_disp1_0);
868 sclk = get_pll_clk(MPLL);
870 sclk = get_pll_clk(EPLL);
872 sclk = get_pll_clk(VPLL);
880 ratio = readl(&clk->div_disp1_0);
883 pclk = sclk / (ratio + 1);
888 void exynos4_set_lcd_clk(void)
890 struct exynos4_clock *clk =
891 (struct exynos4_clock *)samsung_get_base_clock();
892 unsigned int cfg = 0;
904 cfg = readl(&clk->gate_block);
906 writel(cfg, &clk->gate_block);
912 * MDNIE_PWM0_SEL [8:11]
914 * set lcd0 src clock 0x6: SCLK_MPLL
916 cfg = readl(&clk->src_lcd0);
919 writel(cfg, &clk->src_lcd0);
929 * Gating all clocks for FIMD0
931 cfg = readl(&clk->gate_ip_lcd0);
933 writel(cfg, &clk->gate_ip_lcd0);
939 * MDNIE_PWM0_RATIO [11:8]
940 * MDNIE_PWM_PRE_RATIO [15:12]
941 * MIPI0_RATIO [19:16]
942 * MIPI0_PRE_RATIO [23:20]
947 writel(cfg, &clk->div_lcd0);
950 void exynos5_set_lcd_clk(void)
952 struct exynos5_clock *clk =
953 (struct exynos5_clock *)samsung_get_base_clock();
954 unsigned int cfg = 0;
966 cfg = readl(&clk->gate_block);
968 writel(cfg, &clk->gate_block);
974 * MDNIE_PWM0_SEL [8:11]
976 * set lcd0 src clock 0x6: SCLK_MPLL
978 cfg = readl(&clk->src_disp1_0);
981 writel(cfg, &clk->src_disp1_0);
991 * Gating all clocks for FIMD0
993 cfg = readl(&clk->gate_ip_disp1);
995 writel(cfg, &clk->gate_ip_disp1);
1000 * MDNIE0_RATIO [7:4]
1001 * MDNIE_PWM0_RATIO [11:8]
1002 * MDNIE_PWM_PRE_RATIO [15:12]
1003 * MIPI0_RATIO [19:16]
1004 * MIPI0_PRE_RATIO [23:20]
1009 writel(cfg, &clk->div_disp1_0);
1012 void exynos4_set_mipi_clk(void)
1014 struct exynos4_clock *clk =
1015 (struct exynos4_clock *)samsung_get_base_clock();
1016 unsigned int cfg = 0;
1022 * MDNIE_PWM0_SEL [8:11]
1024 * set mipi0 src clock 0x6: SCLK_MPLL
1026 cfg = readl(&clk->src_lcd0);
1027 cfg &= ~(0xf << 12);
1029 writel(cfg, &clk->src_lcd0);
1035 * MDNIE_PWM0_MASK [8]
1037 * set src mask mipi0 0x1: Unmask
1039 cfg = readl(&clk->src_mask_lcd0);
1041 writel(cfg, &clk->src_mask_lcd0);
1051 * Gating all clocks for MIPI0
1053 cfg = readl(&clk->gate_ip_lcd0);
1055 writel(cfg, &clk->gate_ip_lcd0);
1060 * MDNIE0_RATIO [7:4]
1061 * MDNIE_PWM0_RATIO [11:8]
1062 * MDNIE_PWM_PRE_RATIO [15:12]
1063 * MIPI0_RATIO [19:16]
1064 * MIPI0_PRE_RATIO [23:20]
1067 cfg &= ~(0xf << 16);
1069 writel(cfg, &clk->div_lcd0);
1075 * exynos5: obtaining the I2C clock
1077 static unsigned long exynos5_get_i2c_clk(void)
1079 struct exynos5_clock *clk =
1080 (struct exynos5_clock *)samsung_get_base_clock();
1081 unsigned long aclk_66, aclk_66_pre, sclk;
1084 sclk = get_pll_clk(MPLL);
1086 ratio = (readl(&clk->div_top1)) >> 24;
1088 aclk_66_pre = sclk / (ratio + 1);
1089 ratio = readl(&clk->div_top0);
1091 aclk_66 = aclk_66_pre / (ratio + 1);
1095 int exynos5_set_epll_clk(unsigned long rate)
1097 unsigned int epll_con, epll_con_k;
1099 unsigned int lockcnt;
1101 struct exynos5_clock *clk =
1102 (struct exynos5_clock *)samsung_get_base_clock();
1104 epll_con = readl(&clk->epll_con0);
1105 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1106 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1107 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1108 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1109 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1111 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1112 if (exynos5_epll_div[i].freq_out == rate)
1116 if (i == ARRAY_SIZE(exynos5_epll_div))
1119 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1120 epll_con |= exynos5_epll_div[i].en_lock_det <<
1121 EPLL_CON0_LOCK_DET_EN_SHIFT;
1122 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1123 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1124 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1127 * Required period ( in cycles) to genarate a stable clock output.
1128 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1129 * frequency input (as per spec)
1131 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1133 writel(lockcnt, &clk->epll_lock);
1134 writel(epll_con, &clk->epll_con0);
1135 writel(epll_con_k, &clk->epll_con1);
1137 start = get_timer(0);
1139 while (!(readl(&clk->epll_con0) &
1140 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1141 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1142 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1149 void exynos5_set_i2s_clk_source(void)
1151 struct exynos5_clock *clk =
1152 (struct exynos5_clock *)samsung_get_base_clock();
1154 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1155 (CLK_SRC_SCLK_EPLL));
1158 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1159 unsigned int dst_frq)
1161 struct exynos5_clock *clk =
1162 (struct exynos5_clock *)samsung_get_base_clock();
1165 if ((dst_frq == 0) || (src_frq == 0)) {
1166 debug("%s: Invalid requency input for prescaler\n", __func__);
1167 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1171 div = (src_frq / dst_frq);
1172 if (div > AUDIO_1_RATIO_MASK) {
1173 debug("%s: Frequency ratio is out of range\n", __func__);
1174 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1177 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1178 (div & AUDIO_1_RATIO_MASK));
1183 * Linearly searches for the most accurate main and fine stage clock scalars
1184 * (divisors) for a specified target frequency and scalar bit sizes by checking
1185 * all multiples of main_scalar_bits values. Will always return scalars up to or
1186 * slower than target.
1188 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1189 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1190 * @param input_freq Clock frequency to be scaled in Hz
1191 * @param target_freq Desired clock frequency in Hz
1192 * @param best_fine_scalar Pointer to store the fine stage divisor
1194 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1197 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1198 unsigned int fine_scalar_bits, unsigned int input_rate,
1199 unsigned int target_rate, unsigned int *best_fine_scalar)
1202 int best_main_scalar = -1;
1203 unsigned int best_error = target_rate;
1204 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1205 const unsigned int loops = 1 << main_scaler_bits;
1207 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1210 assert(best_fine_scalar != NULL);
1211 assert(main_scaler_bits <= fine_scalar_bits);
1213 *best_fine_scalar = 1;
1215 if (input_rate == 0 || target_rate == 0)
1218 if (target_rate >= input_rate)
1221 for (i = 1; i <= loops; i++) {
1222 const unsigned int effective_div = max(min(input_rate / i /
1223 target_rate, cap), 1);
1224 const unsigned int effective_rate = input_rate / i /
1226 const int error = target_rate - effective_rate;
1228 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1229 effective_rate, error);
1231 if (error >= 0 && error <= best_error) {
1233 best_main_scalar = i;
1234 *best_fine_scalar = effective_div;
1238 return best_main_scalar;
1241 static int exynos5_set_spi_clk(enum periph_id periph_id,
1244 struct exynos5_clock *clk =
1245 (struct exynos5_clock *)samsung_get_base_clock();
1248 unsigned shift, pre_shift;
1249 unsigned mask = 0xff;
1252 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1254 debug("%s: Cannot set clock rate for periph %d",
1255 __func__, periph_id);
1261 switch (periph_id) {
1262 case PERIPH_ID_SPI0:
1263 reg = &clk->div_peric1;
1267 case PERIPH_ID_SPI1:
1268 reg = &clk->div_peric1;
1272 case PERIPH_ID_SPI2:
1273 reg = &clk->div_peric2;
1277 case PERIPH_ID_SPI3:
1278 reg = &clk->sclk_div_isp;
1282 case PERIPH_ID_SPI4:
1283 reg = &clk->sclk_div_isp;
1288 debug("%s: Unsupported peripheral ID %d\n", __func__,
1292 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1293 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1298 static unsigned long exynos4_get_i2c_clk(void)
1300 struct exynos4_clock *clk =
1301 (struct exynos4_clock *)samsung_get_base_clock();
1302 unsigned long sclk, aclk_100;
1305 sclk = get_pll_clk(APLL);
1307 ratio = (readl(&clk->div_top)) >> 4;
1309 aclk_100 = sclk / (ratio + 1);
1313 unsigned long get_pll_clk(int pllreg)
1315 if (cpu_is_exynos5())
1316 return exynos5_get_pll_clk(pllreg);
1318 if (proid_is_exynos4412())
1319 return exynos4x12_get_pll_clk(pllreg);
1320 return exynos4_get_pll_clk(pllreg);
1324 unsigned long get_arm_clk(void)
1326 if (cpu_is_exynos5())
1327 return exynos5_get_arm_clk();
1329 if (proid_is_exynos4412())
1330 return exynos4x12_get_arm_clk();
1331 return exynos4_get_arm_clk();
1335 unsigned long get_i2c_clk(void)
1337 if (cpu_is_exynos5()) {
1338 return exynos5_get_i2c_clk();
1339 } else if (cpu_is_exynos4()) {
1340 return exynos4_get_i2c_clk();
1342 debug("I2C clock is not set for this CPU\n");
1347 unsigned long get_pwm_clk(void)
1349 if (cpu_is_exynos5())
1350 return clock_get_periph_rate(PERIPH_ID_PWM0);
1352 if (proid_is_exynos4412())
1353 return exynos4x12_get_pwm_clk();
1354 return exynos4_get_pwm_clk();
1358 unsigned long get_uart_clk(int dev_index)
1360 if (cpu_is_exynos5())
1361 return exynos5_get_uart_clk(dev_index);
1363 if (proid_is_exynos4412())
1364 return exynos4x12_get_uart_clk(dev_index);
1365 return exynos4_get_uart_clk(dev_index);
1369 unsigned long get_mmc_clk(int dev_index)
1371 if (cpu_is_exynos5())
1372 return exynos5_get_mmc_clk(dev_index);
1374 return exynos4_get_mmc_clk(dev_index);
1377 void set_mmc_clk(int dev_index, unsigned int div)
1379 if (cpu_is_exynos5())
1380 exynos5_set_mmc_clk(dev_index, div);
1382 if (proid_is_exynos4412())
1383 exynos4x12_set_mmc_clk(dev_index, div);
1384 exynos4_set_mmc_clk(dev_index, div);
1388 unsigned long get_lcd_clk(void)
1390 if (cpu_is_exynos4())
1391 return exynos4_get_lcd_clk();
1393 return exynos5_get_lcd_clk();
1396 void set_lcd_clk(void)
1398 if (cpu_is_exynos4())
1399 exynos4_set_lcd_clk();
1401 exynos5_set_lcd_clk();
1404 void set_mipi_clk(void)
1406 if (cpu_is_exynos4())
1407 exynos4_set_mipi_clk();
1410 int set_spi_clk(int periph_id, unsigned int rate)
1412 if (cpu_is_exynos5())
1413 return exynos5_set_spi_clk(periph_id, rate);
1418 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
1421 if (cpu_is_exynos5())
1422 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
1427 void set_i2s_clk_source(void)
1429 if (cpu_is_exynos5())
1430 exynos5_set_i2s_clk_source();
1433 int set_epll_clk(unsigned long rate)
1435 if (cpu_is_exynos5())
1436 return exynos5_set_epll_clk(rate);