1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Broadcom Corporation.
8 * bcm281xx architecture clock framework
15 #include <linux/delay.h>
16 #include <linux/errno.h>
18 #include <asm/arch/sysmap.h>
19 #include <asm/kona-common/clk.h>
22 #define CLK_WR_ACCESS_PASSWORD 0x00a5a501
23 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
24 #define POLICY_CTL_GO 1 /* Load and refresh policy masks */
25 #define POLICY_CTL_GO_ATL 4 /* Active Load */
28 int clk_get_and_enable(char *clkstr)
33 debug("%s: %s\n", __func__, clkstr);
41 printf("%s: Couldn't find %s\n", __func__, clkstr);
48 * Poll a register in a CCU's address space, returning when the
49 * specified bit in that register's value is set (or clear). Delay
50 * a microsecond after each read of the register. Returns true if
51 * successful, or false if we gave up trying.
53 * Caller must ensure the CCU lock is held.
55 #define CLK_GATE_DELAY_USEC 2000
56 static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
59 u32 bit_mask = 1 << bit;
61 for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
65 val = readl(base + offset);
66 bit_val = (val & bit_mask) ? 1 : 0;
68 return 0; /* success */
72 debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
73 __func__, base + offset, bit, want);
78 /* Enable a peripheral clock */
79 static int peri_clk_enable(struct clk *c, int enable)
83 struct peri_clock *peri_clk = to_peri_clk(c);
84 struct peri_clk_data *cd = peri_clk->data;
85 struct bcm_clk_gate *gate = &cd->gate;
86 void *base = (void *)c->ccu_clk_mgr_base;
89 debug("%s: %s\n", __func__, c->name);
91 clk_get_rate(c); /* Make sure rate and sel are filled in */
94 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
97 debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
98 __func__, c->name, c->rate, c->div, c->sel,
102 * clkgate - only software controllable gates are
103 * supported by u-boot which includes all clocks
104 * that matter. This avoids bringing in a lot of extra
105 * complexity as done in the kernel framework.
107 if (gate_exists(gate)) {
108 reg = readl(base + cd->gate.offset);
109 reg |= (1 << cd->gate.en_bit);
110 writel(reg, base + cd->gate.offset);
113 /* div and pll select */
114 if (divider_exists(&cd->div)) {
115 reg = readl(base + cd->div.offset);
116 bitfield_replace(reg, cd->div.shift, cd->div.width,
118 writel(reg, base + cd->div.offset);
121 /* frequency selector */
122 if (selector_exists(&cd->sel)) {
123 reg = readl(base + cd->sel.offset);
124 bitfield_replace(reg, cd->sel.shift, cd->sel.width,
126 writel(reg, base + cd->sel.offset);
130 if (trigger_exists(&cd->trig)) {
131 writel((1 << cd->trig.bit), base + cd->trig.offset);
133 /* wait for trigger status bit to go to 0 */
134 ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
139 /* wait for running (status_bit = 1) */
140 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
144 debug("%s disable clock %s\n", __func__, c->name);
147 reg = readl(base + cd->gate.offset);
148 reg &= ~(1 << cd->gate.en_bit);
149 writel(reg, base + cd->gate.offset);
151 /* wait for stop (status_bit = 0) */
152 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
156 writel(0, base + WR_ACCESS_OFFSET);
161 /* Set the rate of a peripheral clock */
162 static int peri_clk_set_rate(struct clk *c, unsigned long rate)
167 unsigned long new_rate = 0, div = 1;
168 struct peri_clock *peri_clk = to_peri_clk(c);
169 struct peri_clk_data *cd = peri_clk->data;
172 debug("%s: %s\n", __func__, c->name);
176 for (clock = cd->clocks; *clock; clock++, i++) {
177 struct refclk *ref = refclk_str_to_clk(*clock);
179 printf("%s: Lookup of %s failed\n", __func__, *clock);
183 /* round to the new rate */
184 div = ref->clk.rate / rate;
188 new_rate = ref->clk.rate / div;
190 /* get the min diff */
191 if (abs(new_rate - rate) < diff) {
192 diff = abs(new_rate - rate);
194 c->parent = &ref->clk;
200 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
201 c->name, c->rate, c->div, c->sel, c->parent->rate);
205 /* Get the rate of a peripheral clock */
206 static unsigned long peri_clk_get_rate(struct clk *c)
208 struct peri_clock *peri_clk = to_peri_clk(c);
209 struct peri_clk_data *cd = peri_clk->data;
210 void *base = (void *)c->ccu_clk_mgr_base;
216 debug("%s: %s\n", __func__, c->name);
217 if (selector_exists(&cd->sel)) {
218 reg = readl(base + cd->sel.offset);
219 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
222 * For peri clocks that don't have a selector, the single
223 * reference clock will always exist at index 0.
228 if (divider_exists(&cd->div)) {
229 reg = readl(base + cd->div.offset);
230 div = bitfield_extract(reg, cd->div.shift, cd->div.width);
235 ref = refclk_str_to_clk(clock[c->sel]);
237 printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
241 c->parent = &ref->clk;
243 c->rate = c->parent->rate / c->div;
244 debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
245 c->parent->rate, div, c->sel, c->rate);
250 /* Peripheral clock operations */
251 struct clk_ops peri_clk_ops = {
252 .enable = peri_clk_enable,
253 .set_rate = peri_clk_set_rate,
254 .get_rate = peri_clk_get_rate,
257 /* Enable a CCU clock */
258 static int ccu_clk_enable(struct clk *c, int enable)
260 struct ccu_clock *ccu_clk = to_ccu_clk(c);
261 void *base = (void *)c->ccu_clk_mgr_base;
265 debug("%s: %s\n", __func__, c->name);
267 return -EINVAL; /* CCU clock cannot shutdown */
270 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
272 /* config enable for policy engine */
273 writel(1, base + ccu_clk->lvm_en_offset);
275 /* wait for bit to go to 0 */
276 ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
281 if (!ccu_clk->freq_bit_shift)
282 ccu_clk->freq_bit_shift = 8;
284 /* Set frequency id for each of the 4 policies */
285 reg = ccu_clk->freq_id |
286 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
287 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
288 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
289 writel(reg, base + ccu_clk->policy_freq_offset);
291 /* enable all clock mask */
292 writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
293 writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
294 writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
295 writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
297 if (ccu_clk->num_policy_masks == 2) {
298 writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
299 writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
300 writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
301 writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
304 /* start policy engine */
305 reg = readl(base + ccu_clk->policy_ctl_offset);
306 reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
307 writel(reg, base + ccu_clk->policy_ctl_offset);
309 /* wait till started */
310 ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
315 writel(0, base + WR_ACCESS_OFFSET);
320 /* Get the CCU clock rate */
321 static unsigned long ccu_clk_get_rate(struct clk *c)
323 struct ccu_clock *ccu_clk = to_ccu_clk(c);
324 debug("%s: %s\n", __func__, c->name);
325 c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
329 /* CCU clock operations */
330 struct clk_ops ccu_clk_ops = {
331 .enable = ccu_clk_enable,
332 .get_rate = ccu_clk_get_rate,
335 /* Enable a bus clock */
336 static int bus_clk_enable(struct clk *c, int enable)
338 struct bus_clock *bus_clk = to_bus_clk(c);
339 struct bus_clk_data *cd = bus_clk->data;
340 void *base = (void *)c->ccu_clk_mgr_base;
344 debug("%s: %s\n", __func__, c->name);
346 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
349 reg = readl(base + cd->gate.offset);
350 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
351 debug("%s already %s\n", c->name,
352 enable ? "enabled" : "disabled");
354 int want = (enable) ? 1 : 0;
355 reg |= (1 << cd->gate.hw_sw_sel_bit);
358 reg |= (1 << cd->gate.en_bit);
360 reg &= ~(1 << cd->gate.en_bit);
362 writel(reg, base + cd->gate.offset);
363 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
370 writel(0, base + WR_ACCESS_OFFSET);
375 /* Get the rate of a bus clock */
376 static unsigned long bus_clk_get_rate(struct clk *c)
378 struct bus_clock *bus_clk = to_bus_clk(c);
379 struct ccu_clock *ccu_clk;
381 debug("%s: %s\n", __func__, c->name);
382 ccu_clk = to_ccu_clk(c->parent);
384 c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
385 c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
389 /* Bus clock operations */
390 struct clk_ops bus_clk_ops = {
391 .enable = bus_clk_enable,
392 .get_rate = bus_clk_get_rate,
395 /* Enable a reference clock */
396 static int ref_clk_enable(struct clk *c, int enable)
398 debug("%s: %s\n", __func__, c->name);
402 /* Reference clock operations */
403 struct clk_ops ref_clk_ops = {
404 .enable = ref_clk_enable,
408 * clk.h implementation follows
411 /* Initialize the clock framework */
414 debug("%s:\n", __func__);
418 /* Get a clock handle, give a name string */
419 struct clk *clk_get(const char *con_id)
422 struct clk_lookup *clk_tblp;
424 debug("%s: %s\n", __func__, con_id);
426 clk_tblp = arch_clk_tbl;
427 for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
428 if (clk_tblp->con_id) {
429 if (!con_id || strcmp(clk_tblp->con_id, con_id))
431 return clk_tblp->clk;
438 int clk_enable(struct clk *c)
442 debug("%s: %s\n", __func__, c->name);
443 if (!c->ops || !c->ops->enable)
446 /* enable parent clock first */
448 ret = clk_enable(c->parent);
455 ret = c->ops->enable(c, 1);
461 /* Disable a clock */
462 void clk_disable(struct clk *c)
464 debug("%s: %s\n", __func__, c->name);
465 if (!c->ops || !c->ops->enable)
470 c->ops->enable(c, 0);
475 clk_disable(c->parent);
478 /* Get the clock rate */
479 unsigned long clk_get_rate(struct clk *c)
483 if (!c || !c->ops || !c->ops->get_rate)
485 debug("%s: %s\n", __func__, c->name);
487 rate = c->ops->get_rate(c);
488 debug("%s: rate = %ld\n", __func__, rate);
492 /* Set the clock rate */
493 int clk_set_rate(struct clk *c, unsigned long rate)
497 if (!c || !c->ops || !c->ops->set_rate)
499 debug("%s: %s rate=%ld\n", __func__, c->name, rate);
504 ret = c->ops->set_rate(c, rate);
509 /* Not required for this arch */
511 long clk_round_rate(struct clk *clk, unsigned long rate);
512 int clk_set_parent(struct clk *clk, struct clk *parent);
513 struct clk *clk_get_parent(struct clk *clk);