4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/clock.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
29 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
30 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
35 /* dram_init must store complete ramsize in gd->ram_size */
36 gd->ram_size = get_ram_size(
37 (void *)CONFIG_SYS_SDRAM_BASE,
38 CONFIG_MAX_RAM_BANK_SIZE);
42 void dram_init_banksize(void)
44 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
45 gd->bd->bi_dram[0].size = gd->ram_size;
49 #ifdef CONFIG_SPL_BUILD
50 static const struct ddr_data ddr2_data = {
51 .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
52 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
53 .datardsratio1 = DDR2_RD_DQS>>2,
54 .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
55 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
56 .datawdsratio1 = DDR2_WR_DQS>>2,
57 .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
58 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
59 .datawiratio1 = DDR2_PHY_WRLVL>>2,
60 .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
61 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
62 .datagiratio1 = DDR2_PHY_GATELVL>>2,
63 .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
64 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
65 .datafwsratio1 = DDR2_PHY_FIFO_WE>>2,
66 .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
67 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
68 .datawrsratio1 = DDR2_PHY_WR_DATA>>2,
69 .datadldiff0 = PHY_DLL_LOCK_DIFF,
72 static const struct cmd_control ddr2_cmd_ctrl_data = {
73 .cmd0csratio = DDR2_RATIO,
74 .cmd0csforce = CMD_FORCE,
75 .cmd0csdelay = CMD_DELAY,
76 .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
77 .cmd0iclkout = DDR2_INVERT_CLKOUT,
79 .cmd1csratio = DDR2_RATIO,
80 .cmd1csforce = CMD_FORCE,
81 .cmd1csdelay = CMD_DELAY,
82 .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
83 .cmd1iclkout = DDR2_INVERT_CLKOUT,
85 .cmd2csratio = DDR2_RATIO,
86 .cmd2csforce = CMD_FORCE,
87 .cmd2csdelay = CMD_DELAY,
88 .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
89 .cmd2iclkout = DDR2_INVERT_CLKOUT,
92 static void config_vtp(void)
94 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
95 &vtpreg->vtp0ctrlreg);
96 writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
97 &vtpreg->vtp0ctrlreg);
98 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
99 &vtpreg->vtp0ctrlreg);
102 while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
107 static void config_emif_ddr2(void)
110 struct sdram_config cfg;
111 struct sdram_timing tmg;
112 struct ddr_phy_control phyc;
114 /*Program EMIF0 CFG Registers*/
115 phyc.reg = EMIF_READ_LATENCY;
116 phyc.reg_sh = EMIF_READ_LATENCY;
117 phyc.reg2 = EMIF_READ_LATENCY;
119 tmg.time1 = EMIF_TIM1;
120 tmg.time1_sh = EMIF_TIM1;
121 tmg.time2 = EMIF_TIM2;
122 tmg.time2_sh = EMIF_TIM2;
123 tmg.time3 = EMIF_TIM3;
124 tmg.time3_sh = EMIF_TIM3;
126 cfg.sdrcr = EMIF_SDCFG;
127 cfg.sdrcr2 = EMIF_SDCFG;
128 cfg.refresh = EMIF_SDREF;
129 cfg.refresh_sh = EMIF_SDREF;
131 /* Program EMIF instance */
132 ret = config_ddr_phy(&phyc);
134 printf("Couldn't configure phyc\n");
137 ret = set_sdram_timings(&tmg);
139 printf("Couldn't configure timings\n");
141 ret = config_sdram(&cfg);
143 printf("Couldn't configure SDRAM\n");
146 void config_ddr(void)
148 struct ddr_ioctrl ioctrl;
150 enable_emif_clocks();
154 config_cmd_ctrl(&ddr2_cmd_ctrl_data);
156 config_ddr_data(0, &ddr2_data);
157 config_ddr_data(1, &ddr2_data);
159 writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
160 writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
162 ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
163 ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
164 ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
165 ioctrl.data1ctl = DDR_IOCTRL_VALUE;
166 ioctrl.data2ctl = DDR_IOCTRL_VALUE;
168 config_io_ctrl(&ioctrl);
170 writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
171 writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);