4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/ddr_defs.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
20 DECLARE_GLOBAL_DATA_PTR;
24 /* dram_init must store complete ramsize in gd->ram_size */
25 gd->ram_size = get_ram_size(
26 (void *)CONFIG_SYS_SDRAM_BASE,
27 CONFIG_MAX_RAM_BANK_SIZE);
31 void dram_init_banksize(void)
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34 gd->bd->bi_dram[0].size = gd->ram_size;
38 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
40 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
41 (struct dmm_lisa_map_regs *)DMM_BASE;
44 static struct vtp_reg *vtpreg[2] = {
45 (struct vtp_reg *)VTP0_CTRL_ADDR,
46 (struct vtp_reg *)VTP1_CTRL_ADDR};
49 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
53 void config_dmm(const struct dmm_lisa_map_regs *regs)
57 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
58 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
59 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
60 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
62 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
63 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
64 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
65 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
70 static void config_vtp(int nr)
72 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
73 &vtpreg[nr]->vtp0ctrlreg);
74 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
75 &vtpreg[nr]->vtp0ctrlreg);
76 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
77 &vtpreg[nr]->vtp0ctrlreg);
80 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
86 void __weak ddr_pll_config(unsigned int ddrpll_m)
90 void config_ddr(unsigned int pll, unsigned int ioctrl,
91 const struct ddr_data *data, const struct cmd_control *ctrl,
92 const struct emif_regs *regs, int nr)
98 config_cmd_ctrl(ctrl, nr);
100 config_ddr_data(data, nr);
102 config_io_ctrl(ioctrl);
104 /* Set CKE to be controlled by EMIF/DDR PHY */
105 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
108 /* Program EMIF instance */
109 config_ddr_phy(regs, nr);
110 set_sdram_timings(regs, nr);
111 config_sdram(regs, nr);