4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/ddr_defs.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
20 DECLARE_GLOBAL_DATA_PTR;
24 /* dram_init must store complete ramsize in gd->ram_size */
25 gd->ram_size = get_ram_size(
26 (void *)CONFIG_SYS_SDRAM_BASE,
27 CONFIG_MAX_RAM_BANK_SIZE);
31 void dram_init_banksize(void)
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34 gd->bd->bi_dram[0].size = gd->ram_size;
38 #ifdef CONFIG_SPL_BUILD
39 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
40 (struct dmm_lisa_map_regs *)DMM_BASE;
41 static struct vtp_reg *vtpreg[2] = {
42 (struct vtp_reg *)VTP0_CTRL_ADDR,
43 (struct vtp_reg *)VTP1_CTRL_ADDR};
45 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
48 void config_dmm(const struct dmm_lisa_map_regs *regs)
52 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
53 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
54 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
55 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
57 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
58 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
59 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
60 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
63 static void config_vtp(int nr)
65 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
66 &vtpreg[nr]->vtp0ctrlreg);
67 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
68 &vtpreg[nr]->vtp0ctrlreg);
69 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
70 &vtpreg[nr]->vtp0ctrlreg);
73 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
78 void config_ddr(unsigned int pll, unsigned int ioctrl,
79 const struct ddr_data *data, const struct cmd_control *ctrl,
80 const struct emif_regs *regs, int nr)
85 config_cmd_ctrl(ctrl, nr);
87 config_ddr_data(data, nr);
89 config_io_ctrl(ioctrl);
91 /* Set CKE to be controlled by EMIF/DDR PHY */
92 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
95 /* Program EMIF instance */
96 config_ddr_phy(regs, nr);
97 set_sdram_timings(regs, nr);
98 config_sdram(regs, nr);