4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
31 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
32 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
36 /* dram_init must store complete ramsize in gd->ram_size */
37 gd->ram_size = get_ram_size(
38 (void *)CONFIG_SYS_SDRAM_BASE,
39 CONFIG_MAX_RAM_BANK_SIZE);
43 void dram_init_banksize(void)
45 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
46 gd->bd->bi_dram[0].size = gd->ram_size;
50 #ifdef CONFIG_SPL_BUILD
51 static const struct ddr_data ddr2_data = {
52 .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
53 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
54 .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
55 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
56 .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
57 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
58 .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
59 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
60 .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
61 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
62 .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
63 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
64 .datadldiff0 = PHY_DLL_LOCK_DIFF,
67 static const struct cmd_control ddr2_cmd_ctrl_data = {
68 .cmd0csratio = DDR2_RATIO,
69 .cmd0csforce = CMD_FORCE,
70 .cmd0csdelay = CMD_DELAY,
71 .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
72 .cmd0iclkout = DDR2_INVERT_CLKOUT,
74 .cmd1csratio = DDR2_RATIO,
75 .cmd1csforce = CMD_FORCE,
76 .cmd1csdelay = CMD_DELAY,
77 .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
78 .cmd1iclkout = DDR2_INVERT_CLKOUT,
80 .cmd2csratio = DDR2_RATIO,
81 .cmd2csforce = CMD_FORCE,
82 .cmd2csdelay = CMD_DELAY,
83 .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
84 .cmd2iclkout = DDR2_INVERT_CLKOUT,
87 static const struct emif_regs ddr2_emif_reg_data = {
88 .sdram_config = DDR2_EMIF_SDCFG,
89 .ref_ctrl = DDR2_EMIF_SDREF,
90 .sdram_tim1 = DDR2_EMIF_TIM1,
91 .sdram_tim2 = DDR2_EMIF_TIM2,
92 .sdram_tim3 = DDR2_EMIF_TIM3,
93 .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
96 static void config_vtp(void)
98 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
99 &vtpreg->vtp0ctrlreg);
100 writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
101 &vtpreg->vtp0ctrlreg);
102 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
103 &vtpreg->vtp0ctrlreg);
106 while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
111 void config_ddr(short ddr_type)
113 enable_emif_clocks();
115 if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
119 config_cmd_ctrl(&ddr2_cmd_ctrl_data);
121 config_ddr_data(0, &ddr2_data);
122 config_ddr_data(1, &ddr2_data);
124 writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
125 writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
127 config_io_ctrl(DDR2_IOCTRL_VALUE);
129 /* Set CKE to be controlled by EMIF/DDR PHY */
130 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
132 /* Program EMIF instance */
133 config_ddr_phy(&ddr2_emif_reg_data);
134 set_sdram_timings(&ddr2_emif_reg_data);
135 config_sdram(&ddr2_emif_reg_data);