4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/ddr_defs.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
20 DECLARE_GLOBAL_DATA_PTR;
24 /* dram_init must store complete ramsize in gd->ram_size */
25 gd->ram_size = get_ram_size(
26 (void *)CONFIG_SYS_SDRAM_BASE,
27 CONFIG_MAX_RAM_BANK_SIZE);
31 void dram_init_banksize(void)
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34 gd->bd->bi_dram[0].size = gd->ram_size;
38 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
40 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
41 (struct dmm_lisa_map_regs *)DMM_BASE;
44 static struct vtp_reg *vtpreg[2] = {
45 (struct vtp_reg *)VTP0_CTRL_ADDR,
46 (struct vtp_reg *)VTP1_CTRL_ADDR};
49 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
52 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
53 static struct cm_device_inst *cm_device =
54 (struct cm_device_inst *)CM_DEVICE_INST;
58 void config_dmm(const struct dmm_lisa_map_regs *regs)
62 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
63 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
64 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
65 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
67 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
68 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
69 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
70 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
75 static void config_vtp(int nr)
77 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
78 &vtpreg[nr]->vtp0ctrlreg);
79 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
80 &vtpreg[nr]->vtp0ctrlreg);
81 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
82 &vtpreg[nr]->vtp0ctrlreg);
85 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
91 void __weak ddr_pll_config(unsigned int ddrpll_m)
95 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
96 const struct ddr_data *data, const struct cmd_control *ctrl,
97 const struct emif_regs *regs, int nr)
100 #ifndef CONFIG_TI816X
103 config_cmd_ctrl(ctrl, nr);
105 config_ddr_data(data, nr);
107 config_io_ctrl(ioregs);
109 /* Set CKE to be controlled by EMIF/DDR PHY */
110 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
113 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
114 while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
116 writel(0x80000000, &ddrctrl->ddrioctrl);
118 config_io_ctrl(ioregs);
120 /* Set CKE to be controlled by EMIF/DDR PHY */
121 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
124 /* Program EMIF instance */
125 config_ddr_phy(regs, nr);
126 set_sdram_timings(regs, nr);
127 if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
128 config_sdram_emif4d5(regs, nr);
130 config_sdram(regs, nr);